* Re: [kernel] Hello list
[not found] <1f7722e8-2faf-414d-84df-8dbfd9913552@ime.usp.br>
@ 2026-03-18 13:21 ` Rafael Passos
2026-03-18 13:28 ` [kernel] [PATCH] drm/amd/display: fix resuming from S3 sleep for Renoir iGPU Rafael Passos
0 siblings, 1 reply; 2+ messages in thread
From: Rafael Passos @ 2026-03-18 13:21 UTC (permalink / raw)
To: kernel
Testing
On 17 March 2026 09:17:56 GMT-03:00, Rafael Passos <rcpassos@ime.usp.br> wrote:
>Test email for Kernel @ ime list
>
Rafael Passos
Software Engineer
São Paulo, Brasil
--
kernel mailing list
kernel@lists.ime.usp.br
https://lists.ime.usp.br/listinfo/kernel
^ permalink raw reply [flat|nested] 2+ messages in thread
* [kernel] [PATCH] drm/amd/display: fix resuming from S3 sleep for Renoir iGPU
2026-03-18 13:21 ` [kernel] Hello list Rafael Passos
@ 2026-03-18 13:28 ` Rafael Passos
0 siblings, 0 replies; 2+ messages in thread
From: Rafael Passos @ 2026-03-18 13:28 UTC (permalink / raw)
To: rcpassos; +Cc: kernel, Rafael Passos
The previous commit introduced a change where the dcn21_s0i3_golden_init_wa
function used to read the MICROSECOND_TIME_BASE_DIV reg from hwseq, and
now started reading from dccg using dccg2_is_s0i3_golden_init_wa_done.
However, this register is not properly initialized in dccg.
Also, the value was initialized to 0x00120264 by dccg2_init, but
compared to 0x00120464. For this reason, we created a new dccg21_init
with the values used specific for this card.
Fixes: 4c595e75110e ("drm/amd/display: Migrate DCCG registers access from hwseq to dccg component.")
Signed-off-by: Rafael Passos <rafael@rcpassos.me>
Signed-off-by: David Tadokoro <davidbtadokoro@ime.usp.br>
---
.../drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c | 17 ++++++++++++++++-
.../display/dc/resource/dcn21/dcn21_resource.c | 3 ++-
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c
index 75c69348027e..6f96e9c189dc 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c
@@ -96,6 +96,21 @@ static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppcl
dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
}
+void dccg21_init(struct dccg *dccg)
+{
+ struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+ /* Hardcoded register values for DCN21
+ * These are specific to 100Mhz refclk
+ * Different ASICs with different refclk may override this in their own init
+ */
+ REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x00120464);
+ REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x001186a0);
+ REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x0e01003c);
+
+ if (REG(REFCLK_CNTL))
+ REG_WRITE(REFCLK_CNTL, 0);
+}
static const struct dccg_funcs dccg21_funcs = {
.update_dpp_dto = dccg21_update_dpp_dto,
@@ -103,7 +118,7 @@ static const struct dccg_funcs dccg21_funcs = {
.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
.otg_add_pixel = dccg2_otg_add_pixel,
.otg_drop_pixel = dccg2_otg_drop_pixel,
- .dccg_init = dccg2_init,
+ .dccg_init = dccg21_init,
.refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */
.allow_clock_gating = dccg2_allow_clock_gating,
.enable_memory_low_power = dccg2_enable_memory_low_power,
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
index 0f4307f8f3dd..4b107ef2d632 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
@@ -222,7 +222,8 @@ static const struct dce_audio_mask audio_mask = {
};
static const struct dccg_registers dccg_regs = {
- DCCG_COMMON_REG_LIST_DCN_BASE()
+ DCCG_COMMON_REG_LIST_DCN_BASE(),
+ SR(MICROSECOND_TIME_BASE_DIV)
};
static const struct dccg_shift dccg_shift = {
--
2.53.0
--
kernel mailing list
kernel@lists.ime.usp.br
https://lists.ime.usp.br/listinfo/kernel
^ permalink raw reply related [flat|nested] 2+ messages in thread
end of thread, other threads:[~2026-03-18 13:30 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
[not found] <1f7722e8-2faf-414d-84df-8dbfd9913552@ime.usp.br>
2026-03-18 13:21 ` [kernel] Hello list Rafael Passos
2026-03-18 13:28 ` [kernel] [PATCH] drm/amd/display: fix resuming from S3 sleep for Renoir iGPU Rafael Passos
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox