Subject: Re: [PATCH 00/11] arm/arm64: Turning IPIs into normal interrupts

From: Florian Fainelli <[email-masked]>
Date: Fri, 12 Jun 2020 09:57:16 -0700

On 6/12/2020 2:49 AM, Marc Zyngier wrote:
> Hi Florian,
> 
> On Tue, 19 May 2020 10:50:46 -0700
> Florian Fainelli <[email-masked]> wrote:
> 
>> On 5/19/2020 9:17 AM, Marc Zyngier wrote:
>>> For as long as SMP ARM has existed, IPIs have been handled as
>>> something special. The arch code and the interrupt controller exchange
>>> a couple of hooks (one to generate an IPI, another to handle it).
>>>
>>> Although this is perfectly manageable, it prevents the use of features
>>> that we could use if IPIs were Linux IRQs (such as pseudo-NMIs). It
>>> also means that each interrupt controller driver has to follow an
>>> architecture-specific interface instead of just implementing the base
>>> irqchip functionnalities. The arch code also duplicates a number of
>>> things that the core irq code already does (such as calling
>>> set_irq_regs(), irq_enter()...).
>>>
>>> This series tries to remedy this on arm/arm64 by offering a new
>>> registration interface where the irqchip gives the arch code a range
>>> of interrupts to use for IPIs. The arch code requests these as normal
>>> interrupts.
>>>
>>> The bulk of the work is at the interrupt controller level, where all 3
>>> irqchips used on arm64 get converted.
>>>
>>> Finally, the arm64 code drops the legacy registration interface. The
>>> same thing could be done on 32bit as well once the two remaining
>>> irqchips using that interface get converted.
>>>
>>> There is probably more that could be done: statistics are still
>>> architecture-private code, for example, and no attempt is made to
>>> solve that (apart from hidding the IRQs from /proc/interrupt).
>>>
>>> This has been tested on a bunch of 32 and 64bit guests.  
>>
>> Does this patch series change your position on this patch series
>>
>> https://lore.kernel.org/linux-arm-kernel/[email-masked]/T/
>>
>> or is this still a no-no?
> 
> I don't think this series changes anything. There is no easy way to
> reserve SGIs in a way that would work for all combination of OS and FW,
> and the prospect of sending SGIs between S and NS has already been
> dubious (yes, the GIC architecture allows it, but it has been written
> by people who have never designed any large piece of SW).

That is fair enough, we have transitioned since then to using SPIs and
that appears to work nicely for what we want to do without requiring
your patch series.

In premise it is still possible for someone to specify 0x561 as the
first interrupt cell specifier  in the Device Tree in order to specify a
SGI interrupt and this will happily be parsed as a valid interrupt.

It would most likely fail some time later while trying to set the
interrupt type though. I do not think you can do better than this, as
there is no way for you to know the caller of gic_irq_domain_translate()
and reject them.
-- 
Florian

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