From: Vladimir Murzin <vladimir.murzin@arm•com>
To: Zeng Heng <zengheng@huaweicloud•com>,
xuwei5@huawei•com, wangyushan12@huawei•com,
yangyicong@hisilicon•com, maz@kernel•org, yeoreum.yun@arm•com,
miko.lenczewski@arm•com, james.clark@linaro•org, corbet@lwn•net,
skhan@linuxfoundation•org, kuninori.morimoto.gx@renesas•com,
lucaswei@google•com, catalin.marinas@arm•com, broonie@kernel•org,
lpieralisi@kernel•org, thuth@redhat•com, kevin.brodsky@arm•com,
tongtiangen@huawei•com, oupton@kernel•org, ryan.roberts@arm•com,
mark.rutland@arm•com, will@kernel•org, Sascha.Bischoff@arm•com
Cc: linux-arm-kernel@lists•infradead.org, wangkefeng.wang@huawei•com,
linux-doc@vger•kernel.org, linux-kernel@vger•kernel.org
Subject: Re: [PATCH v3 2/2] arm64: kernel: Disable CNP on HiSilicon HIP09
Date: Tue, 2 Jun 2026 10:24:03 +0100 [thread overview]
Message-ID: <0b4cae62-bb4a-4b2c-af4e-0f9d7077961a@arm.com> (raw)
In-Reply-To: <20260601112000.1145391-3-zengheng@huaweicloud.com>
On 6/1/26 12:20, Zeng Heng wrote:
> From: Zeng Heng <zengheng4@huawei•com>
>
> HiSilicon HIP09 implements TLB entry matching behavior that deviates
> from the ARM architecture specification when the CNP (Common not Private)
> bit is set in TTBRx_ELx.
>
> When TTBRx.CNP=1, TLB entries may be incorrectly shared between CPU
> cores, leading to TLB conflicts and stale mappings. This affects
> coherency and can result in incorrect translations.
>
> Add the hardware erratum workaround (Hisilicon erratum 162100125) to
> disable CNP on affected HIP09 cores.
>
> Co-developed-by: Tong Tiangen <tongtiangen@huawei•com>
> Signed-off-by: Tong Tiangen <tongtiangen@huawei•com>
> Signed-off-by: Zeng Heng <zengheng4@huawei•com>
> ---
> Documentation/arch/arm64/silicon-errata.rst | 2 ++
> arch/arm64/Kconfig | 16 ++++++++++++++++
> arch/arm64/kernel/cpu_errata.c | 13 ++++++++++---
> 3 files changed, 28 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
> index 211119ce7adc..cd50059edb85 100644
> --- a/Documentation/arch/arm64/silicon-errata.rst
> +++ b/Documentation/arch/arm64/silicon-errata.rst
> @@ -284,6 +284,8 @@ stable kernels.
> +----------------+-----------------+-----------------+-----------------------------+
> | Hisilicon | Hip09 | #162100801 | HISILICON_ERRATUM_162100801 |
> +----------------+-----------------+-----------------+-----------------------------+
> +| Hisilicon | Hip09 | #162100125 | HISILICON_ERRATUM_162100125 |
> ++----------------+-----------------+-----------------+-----------------------------+
> +----------------+-----------------+-----------------+-----------------------------+
> | Qualcomm Tech. | Kryo/Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
> +----------------+-----------------+-----------------+-----------------------------+
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index f297517a83b9..75638e37883d 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -1273,6 +1273,22 @@ config HISILICON_ERRATUM_162100801
>
> If unsure, say Y.
>
> +config HISILICON_ERRATUM_162100125
> + bool "Hisilicon erratum 162100125"
> + default y
> + select ARM64_WORKAROUND_DISABLE_CNP
> + help
> + On HiSilicon HIP09, TLB entry matching behavior when CNP
> + (TTBRx.CNP=1) is enabled differs from the ARM architecture
> + specification.
> +
> + TLB entries may be incorrectly shared between CPUs, potentially
> + causing TLB conflicts and stale mappings.
> +
> + Disable CNP support for affected HiSilicon HIP09 cores.
> +
> + If unsure, say Y.
> +
> config QCOM_FALKOR_ERRATUM_1003
> bool "Falkor E1003: Incorrect translation due to ASID change"
> default y
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index b0db946568b7..02e0ee5c948c 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -608,6 +608,14 @@ static const struct midr_range erratum_ac04_cpu_23_list[] = {
> };
> #endif
>
> +#ifdef CONFIG_ARM64_WORKAROUND_DISABLE_CNP
> +static const struct midr_range cnp_erratum_cpus[] = {
> + MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
> + MIDR_ALL_VERSIONS(MIDR_HISI_HIP09),
> + {},
> +};
> +#endif
> +
> const struct arm64_cpu_capabilities arm64_errata[] = {
> #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
> {
> @@ -803,10 +811,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
> #endif
> #ifdef CONFIG_ARM64_WORKAROUND_DISABLE_CNP
> {
> - /* NVIDIA Carmel */
> - .desc = "NVIDIA Carmel CNP erratum",
> + .desc = "NVIDIA Carmel CNP erratum, or Hisilicon erratum 162100125",
> .capability = ARM64_WORKAROUND_DISABLE_CNP,
> - ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
> + ERRATA_MIDR_RANGE_LIST(cnp_erratum_cpus),
> },
> #endif
> #ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
> --
> 2.43.0
>
FWIW,
Reviewed-by: Vladimir Murzin <vladimir.murzin@arm•com>
next prev parent reply other threads:[~2026-06-02 9:24 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-01 11:19 [PATCH v3 0/2] arm64: cpufeature: Add WORKAROUND_DISABLE_CNP capability Zeng Heng
2026-06-01 11:19 ` [PATCH v3 1/2] " Zeng Heng
2026-06-02 9:23 ` Vladimir Murzin
2026-06-01 11:20 ` [PATCH v3 2/2] arm64: kernel: Disable CNP on HiSilicon HIP09 Zeng Heng
2026-06-02 9:24 ` Vladimir Murzin [this message]
2026-06-02 15:53 ` Will Deacon
2026-06-03 1:13 ` Zeng Heng
2026-06-02 9:28 ` [PATCH v3 0/2] arm64: cpufeature: Add WORKAROUND_DISABLE_CNP capability Vladimir Murzin
2026-06-02 11:54 ` Wei Xu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=0b4cae62-bb4a-4b2c-af4e-0f9d7077961a@arm.com \
--to=vladimir.murzin@arm$(echo .)com \
--cc=Sascha.Bischoff@arm$(echo .)com \
--cc=broonie@kernel$(echo .)org \
--cc=catalin.marinas@arm$(echo .)com \
--cc=corbet@lwn$(echo .)net \
--cc=james.clark@linaro$(echo .)org \
--cc=kevin.brodsky@arm$(echo .)com \
--cc=kuninori.morimoto.gx@renesas$(echo .)com \
--cc=linux-arm-kernel@lists$(echo .)infradead.org \
--cc=linux-doc@vger$(echo .)kernel.org \
--cc=linux-kernel@vger$(echo .)kernel.org \
--cc=lpieralisi@kernel$(echo .)org \
--cc=lucaswei@google$(echo .)com \
--cc=mark.rutland@arm$(echo .)com \
--cc=maz@kernel$(echo .)org \
--cc=miko.lenczewski@arm$(echo .)com \
--cc=oupton@kernel$(echo .)org \
--cc=ryan.roberts@arm$(echo .)com \
--cc=skhan@linuxfoundation$(echo .)org \
--cc=thuth@redhat$(echo .)com \
--cc=tongtiangen@huawei$(echo .)com \
--cc=wangkefeng.wang@huawei$(echo .)com \
--cc=wangyushan12@huawei$(echo .)com \
--cc=will@kernel$(echo .)org \
--cc=xuwei5@huawei$(echo .)com \
--cc=yangyicong@hisilicon$(echo .)com \
--cc=yeoreum.yun@arm$(echo .)com \
--cc=zengheng@huaweicloud$(echo .)com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox