Subject: Re: [PATCH 06/14] arm64: dts: sparx5: Add basic cpu support

From: Marc Zyngier <[email-masked]>
Date: Fri, 15 May 2020 17:31:40 +0100

[using the correct email address this time]

On 2020-05-15 16:09, Lars Povlsen wrote:
> Marc Zyngier writes:
> 
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know 
>> the content is safe
>> 
>> On 2020-05-13 13:55, Lars Povlsen wrote:
>>> This adds the basic DT structure for the Microchip Sparx5 SoC, and 
>>> the
>>> reference boards, pcb125, pcb134 and pcb135. The two latter have a
>>> NAND vs a eMMC centric variant (as a mount option),
>>> 
>>> Reviewed-by: Alexandre Belloni <[email-masked]>
>>> Signed-off-by: Lars Povlsen <[email-masked]>
>>> ---
>>>  MAINTAINERS                                   |   1 +
>>>  arch/arm64/boot/dts/Makefile                  |   1 +
>>>  arch/arm64/boot/dts/microchip/Makefile        |   4 +
>>>  arch/arm64/boot/dts/microchip/sparx5.dtsi     | 135 
>>> ++++++++++++++++++
>>>  .../boot/dts/microchip/sparx5_pcb125.dts      |  17 +++
>>>  .../boot/dts/microchip/sparx5_pcb134.dts      |  17 +++
>>>  .../dts/microchip/sparx5_pcb134_board.dtsi    |  15 ++
>>>  .../boot/dts/microchip/sparx5_pcb134_emmc.dts |  17 +++
>>>  .../boot/dts/microchip/sparx5_pcb135.dts      |  17 +++
>>>  .../dts/microchip/sparx5_pcb135_board.dtsi    |  15 ++
>>>  .../boot/dts/microchip/sparx5_pcb135_emmc.dts |  17 +++
>>>  .../boot/dts/microchip/sparx5_pcb_common.dtsi |  15 ++
>>>  12 files changed, 271 insertions(+)
>>>  create mode 100644 arch/arm64/boot/dts/microchip/Makefile
>>>  create mode 100644 arch/arm64/boot/dts/microchip/sparx5.dtsi
>>>  create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
>>>  create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
>>>  create mode 100644
>>> arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
>>>  create mode 100644
>>> arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts
>>>  create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
>>>  create mode 100644
>>> arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
>>>  create mode 100644
>>> arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts
>>>  create mode 100644
>>> arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi
>>> 
>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>> index 1b5a18d3dbb9f..5aa28d6e39d4f 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -2084,6 +2084,7 @@ M:      Lars Povlsen 
>>> <[email-masked]>
>>>  M:   Steen Hegelund <[email-masked]>
>>>  M:   Microchip Linux Driver Support <[email-masked]>
>>>  L:   [email-masked] (moderated for
>>> non-subscribers)
>>> +F:   arch/arm64/boot/dts/microchip/
>>>  N:   sparx5
>>>  S:   Supported
>>> 
>>> diff --git a/arch/arm64/boot/dts/Makefile
>>> b/arch/arm64/boot/dts/Makefile
>>> index f19b762c008d8..9680a7f20c307 100644
>>> --- a/arch/arm64/boot/dts/Makefile
>>> +++ b/arch/arm64/boot/dts/Makefile
>>> @@ -17,6 +17,7 @@ subdir-y += intel
>>>  subdir-y += lg
>>>  subdir-y += marvell
>>>  subdir-y += mediatek
>>> +subdir-y += microchip
>>>  subdir-y += nvidia
>>>  subdir-y += qcom
>>>  subdir-y += realtek
>>> diff --git a/arch/arm64/boot/dts/microchip/Makefile
>>> b/arch/arm64/boot/dts/microchip/Makefile
>>> new file mode 100644
>>> index 0000000000000..c6e0313eea0f9
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/microchip/Makefile
>>> @@ -0,0 +1,4 @@
>>> +# SPDX-License-Identifier: GPL-2.0
>>> +dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb125.dtb
>>> +dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb134.dtb 
>>> sparx5_pcb134_emmc.dtb
>>> +dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb135.dtb 
>>> sparx5_pcb135_emmc.dtb
>>> diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
>>> b/arch/arm64/boot/dts/microchip/sparx5.dtsi
>>> new file mode 100644
>>> index 0000000000000..3136b4369f507
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
>>> @@ -0,0 +1,135 @@
>>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>>> +/*
>>> + * Copyright (c) 2020 Microchip Technology Inc. and its 
>>> subsidiaries.
>>> + */
>>> +
>>> +#include <dt-bindings/gpio/gpio.h>
>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +
>>> +/ {
>>> +     compatible = "microchip,sparx5";
>>> +     interrupt-parent = <&gic>;
>>> +     #address-cells = <2>;
>>> +     #size-cells = <1>;
>>> +
>>> +     aliases {
>>> +             serial0 = &uart0;
>>> +             serial1 = &uart1;
>>> +     };
>>> +
>>> +     chosen {
>>> +             stdout-path = "serial0:115200n8";
>>> +     };
>>> +
>>> +     cpus {
>>> +             #address-cells = <2>;
>>> +             #size-cells = <0>;
>>> +             cpu-map {
>>> +                     cluster0 {
>>> +                             core0 {
>>> +                                     cpu = <&cpu0>;
>>> +                             };
>>> +                             core1 {
>>> +                                     cpu = <&cpu1>;
>>> +                             };
>>> +                     };
>>> +             };
>>> +             cpu0: cpu@0 {
>>> +                     compatible = "arm,cortex-a53", "arm,armv8";
>>> +                     device_type = "cpu";
>>> +                     reg = <0x0 0x0>;
>>> +                     enable-method = "spin-table";
>> 
>> Really? This is 2020, not 2012 any more. Surely a new platform
>> boots using PSCI, and not *this*.
>> 
> 
> We don't currently support PSCI. The platform does not have TrustZone,
> hence we don't use ATF.

It does have EL3, as you cannot remove EL3 from A53. Hence it can run
a secure payload, and thus PSCI. TrustZone really is something else,
not directly related to ATF (which will run fine on this HW).

> We use U-Boot as the (only) bootloader, providing the spintable. I 
> looked
> at adding PSCI (in U-Boot) initially, but as most other platforms were
> using ATF the PSCI support was buggy and caused me to go for spintable.

It should be absolutely trivial to fix, and I'd suggest you do that
rather than add this cruft. Even porting ATF to your platform should be
pretty easy.

> Is spintable being deprecated?

It was only ever there to support systems that cannot rely on a more
privileged exception level to power-on the CPUs. There is exactly *one*
CPU of this kind in the wild (Applied Micro's X-Gene). Everything else
should be using PSCI.

Thanks,

         M.
-- 
Jazz is not dead. It just smells funny...

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