Subject: [PSCI DISCUSS] How to implement standby and suspend-to-ram by PSCI

From: [email-masked] (Oliver Neukum)
Date: Tue, 17 May 2016 13:53:56 +0200

On Thu, 2016-05-12 at 09:42 +0000, Hongbo Zhang wrote:
> On our platform we have some shallow states which maps to cpuidle
> well, 
> and we have two more deeper states:
> 
> Sleep state:
> All cores are in WFI state,
> Core cluster is in standby state, e.g. L2 cache is flushed then stops 
> snooping,
> Only those modules which are required to wake up the device still have
> a 
> running clock, other device modules in chip are clock gated.
> 
> Deep sleep state:
> ARM cores and DDR controller are switched off,
> DDR is in self-refresh mode,
> VDD power to off domain IPs are removed, Only the blocks needed to 
> detect wake up and sequence the chip out of deep sleep are on.

For the pm module of the core kernel a low power state is a sleep
state if even one of three conditions is met:

a) a device that can be used for input is not a source of wake ups
b) tasks need to be frozen to enter it
c) the display goes off, while it should be on

Generally runtime PM is better if you can get the same results.
Going to a system sleep state is a necessary evil.

	Regards
		Oliver