From: Dong Aisheng <aisheng.dong@nxp•com>
To: linux-arm-kernel@lists•infradead.org
Cc: Dong Aisheng <aisheng.dong@nxp•com>,
devicetree@vger•kernel.org, dongas86@gmail•com,
catalin.marinas@arm•com, will.deacon@arm•com,
oliver.graute@gmail•com, robh+dt@kernel•org, linux-imx@nxp•com,
kernel@pengutronix•de, fabio.estevam@nxp•com,
Mark Rutland <mark.rutland@arm•com>,
shawnguo@kernel•org
Subject: [PATCH V3 06/15] arm64: dts: imx8: add adma lpcg clocks
Date: Thu, 12 Sep 2019 23:30:43 +0800 [thread overview]
Message-ID: <1568302252-28066-7-git-send-email-aisheng.dong@nxp.com> (raw)
In-Reply-To: <1568302252-28066-1-git-send-email-aisheng.dong@nxp.com>
Add adma lpcg clocks
Cc: Rob Herring <robh+dt@kernel•org>
Cc: Mark Rutland <mark.rutland@arm•com>
Cc: devicetree@vger•kernel.org
Cc: Shawn Guo <shawnguo@kernel•org>
Cc: Sascha Hauer <kernel@pengutronix•de>
Cc: Fabio Estevam <fabio.estevam@nxp•com>
Tested-by: Oliver Graute <oliver.graute@kococonnector•com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp•com>
---
ChangeLog:
v2->v3:
* update to use clock-indices property instead of bit-offset property
v1->v2:
* Use old SCU clock binding temporarily to avoid build warning due to SCU
clock cell will be changed to 2.
* add power domain property
---
arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi | 121 ++++++++++++++++++++++++
1 file changed, 121 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
index 28b8fc9..39dfdcb 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
@@ -4,17 +4,50 @@
* Dong Aisheng <aisheng.dong@nxp•com>
*/
+#include <dt-bindings/firmware/imx/rsrc.h>
+
adma_subsys: bus@59000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x59000000 0x0 0x59000000 0x2000000>;
+ dma_ipg_clk: clock-dma-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <120000000>;
+ clock-output-names = "dma_ipg_clk";
+ };
+
+ /* LPCG clocks */
adma_lpcg: clock-controller@59000000 {
reg = <0x59000000 0x2000000>;
#clock-cells = <1>;
};
+ dsp_lpcg: clock-controller@59580000 {
+ reg = <0x59580000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&dma_ipg_clk>,
+ <&dma_ipg_clk>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
+ <IMX_LPCG_CLK_7>;
+ clock-output-names = "dsp_lpcg_adb_clk",
+ "dsp_lpcg_ipg_clk",
+ "dsp_lpcg_core_clk";
+ power-domains = <&pd IMX_SC_R_DSP>;
+ };
+
+ dsp_ram_lpcg: clock-controller@59590000 {
+ reg = <0x59590000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_4>;
+ clock-output-names = "dsp_ram_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_DSP_RAM>;
+ };
+
adma_dsp: dsp@596e8000 {
compatible = "fsl,imx8qxp-dsp";
reg = <0x596e8000 0x88000>;
@@ -80,6 +113,50 @@ adma_subsys: bus@59000000 {
status = "disabled";
};
+ uart0_lpcg: clock-controller@5a460000 {
+ reg = <0x5a460000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_ADMA_UART0_CLK>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "uart0_lpcg_baud_clk",
+ "uart0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_UART_0>;
+ };
+
+ uart1_lpcg: clock-controller@5a470000 {
+ reg = <0x5a470000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_ADMA_UART1_CLK>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "uart1_lpcg_baud_clk",
+ "uart1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_UART_1>;
+ };
+
+ uart2_lpcg: clock-controller@5a480000 {
+ reg = <0x5a480000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_ADMA_UART2_CLK>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "uart2_lpcg_baud_clk",
+ "uart2_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_UART_2>;
+ };
+
+ uart3_lpcg: clock-controller@5a490000 {
+ reg = <0x5a490000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_ADMA_UART3_CLK>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "uart3_lpcg_baud_clk",
+ "uart3_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_UART_3>;
+ };
+
adma_i2c0: i2c@5a800000 {
reg = <0x5a800000 0x4000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
@@ -127,4 +204,48 @@ adma_subsys: bus@59000000 {
power-domains = <&pd IMX_SC_R_I2C_3>;
status = "disabled";
};
+
+ i2c0_lpcg: clock-controller@5ac00000 {
+ reg = <0x5ac00000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_ADMA_I2C0_CLK>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "i2c0_lpcg_clk",
+ "i2c0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_I2C_0>;
+ };
+
+ i2c1_lpcg: clock-controller@5ac10000 {
+ reg = <0x5ac10000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_ADMA_I2C1_CLK>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "i2c1_lpcg_clk",
+ "i2c1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_I2C_1>;
+ };
+
+ i2c2_lpcg: clock-controller@5ac20000 {
+ reg = <0x5ac20000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_ADMA_I2C2_CLK>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "i2c2_lpcg_clk",
+ "i2c2_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_I2C_2>;
+ };
+
+ i2c3_lpcg: clock-controller@5ac30000 {
+ reg = <0x5ac30000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_ADMA_I2C3_CLK>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "i2c3_lpcg_clk",
+ "i2c3_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_I2C_3>;
+ };
};
--
2.7.4
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next prev parent reply other threads:[~2019-09-12 15:34 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-12 15:30 [PATCH V3 00/15] arm64: dts: imx8: architecture improvement and adding imx8qm support Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 01/15] arm64: dts: imx8qxp: add fallback compatible string for scu pd Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 02/15] arm64: dts: imx8qxp: move scu pd node before scu clock node Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 03/15] arm64: dts: imx8qxp: orginize dts in subsystems Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 04/15] arm64: dts: imx8: add lsio lpcg clocks Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 05/15] arm64: dts: imx8: add conn " Dong Aisheng
2019-09-12 15:30 ` Dong Aisheng [this message]
2019-09-12 15:30 ` [PATCH V3 07/15] arm64: dts: imx8: switch to two cell scu clock binding Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 08/15] arm64: dts: imx8: switch to new lpcg " Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 09/15] arm64: dts: imx8qm: add lsio ss support Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 10/15] arm64: dts: imx8qm: add conn " Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 11/15] arm64: dts: imx8: split adma ss into dma and audio ss Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 12/15] arm64: dts: imx8qm: add dma ss support Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 13/15] arm64: dts: imx: add imx8qm common dts file Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 14/15] arm64: dts: imx: add imx8qm mek support Dong Aisheng
2019-09-12 15:30 ` [PATCH V3 15/15] arm64: defconfig: " Dong Aisheng
2019-09-13 12:16 ` [PATCH V3 00/15] arm64: dts: imx8: architecture improvement and adding imx8qm support Oliver Graute
2019-09-13 16:43 ` Aisheng Dong
2019-09-16 11:22 ` Oliver Graute
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