Subject: [PATCH v4 1/2] Documentation: Documentation for qcom, llcc

From: [email-masked] (rishabhb at codeaurora.org)
Date: Tue, 17 Apr 2018 15:12:42 -0700

On 2018-04-17 10:43, rishabhb at codeaurora.org wrote:
> On 2018-04-16 07:59, Rob Herring wrote:
>> On Tue, Apr 10, 2018 at 01:08:12PM -0700, Rishabh Bhatnagar wrote:
>>> Documentation for last level cache controller device tree bindings,
>>> client bindings usage examples.
>> 
>> "Documentation: Documentation ..."? That wastes a lot of the subject
>> line... The preferred prefix is "dt-bindings: ..."
>> 
>>> 
>>> Signed-off-by: Channagoud Kadabi <[email-masked]>
>>> Signed-off-by: Rishabh Bhatnagar <[email-masked]>
>>> ---
>>>  .../devicetree/bindings/arm/msm/qcom,llcc.txt      | 58 
>>> ++++++++++++++++++++++
>>>  1 file changed, 58 insertions(+)
>>>  create mode 100644 
>>> Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
>>> 
>>> diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt 
>>> b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
>>> new file mode 100644
>>> index 0000000..497cf0f
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
>>> @@ -0,0 +1,58 @@
>>> +== Introduction==
>>> +
>>> +LLCC (Last Level Cache Controller) provides last level of cache 
>>> memory in SOC,
>>> +that can be shared by multiple clients. Clients here are different 
>>> cores in the
>>> +SOC, the idea is to minimize the local caches at the clients and 
>>> migrate to
>>> +common pool of memory
>>> +
>>> +Properties:
>>> +- compatible:
>>> +	 Usage: required
>>> +	 Value type: <string>
>>> +	 Definition: must be "qcom,sdm845-llcc"
>>> +
>>> +- reg:
>>> +	 Usage: required
>>> +	 Value Type: <prop-encoded-array>
>>> +	 Definition: must be addresses and sizes of the LLCC registers
>> 
>> How many address ranges?
>> 
> It consists of just one address range. I'll edit the definition to make
> it more clear.
>>> +
>>> +- #cache-cells:
>> 
>> This is all written as it is a common binding, but it is not one.
>> 
>> You already have most of the configuration data for each client in the
>> driver, I think I'd just put the client connection there too. Is there
>> any variation of this for a given SoC?
>> 
> #cache-cells and max-slices won't change for a given SOC. So you want 
> me
> to hard-code in the driver itself?
> 
I can use of_parse_phandle_with_fixed_args function and fix the number 
of
args as 1 instead of keeping #cache-cells here in DT. Does that look 
fine?
>>> +	 Usage: required
>>> +	 Value Type: <u32>
>>> +	 Definition: Number of cache cells, must be 1
>>> +
>>> +- max-slices:
>>> +	 usage: required
>>> +	 Value Type: <u32>
>>> +	 Definition: Number of cache slices supported by hardware
>> 
>> What's a slice?
>> 
> System cache memory provided by LLCC is divided into smaller chunks
> called slices. Each slice has its associated size and ID. Clients can
> query slice details, activate and deactivate them.
>>> +
>>> +Example:
>>> +
>>> +	llcc: qcom,llcc at 1100000 {
>>> +		compatible = "qcom,sdm845-llcc";
>>> +		reg = <0x1100000 0x250000>;
>>> +		#cache-cells = <1>;
>>> +		max-slices = <32>;
>>> +	};
>>> +
>>> +== Client ==
>>> +
>>> +Properties:
>>> +- cache-slice-names:
>>> +	 Usage: required
>>> +	 Value type: <stringlist>
>>> +	 Definition: A set of names that identify the usecase names of a
>>> +			client that uses cache slice. These strings are
>>> +			used to look up the cache slice entries by name.
>>> +
>>> +- cache-slices:
>>> +	 Usage: required
>>> +	 Value type: <prop-encoded-array>
>>> +	 Definition: The tuple has phandle to llcc device as the first
>>> +			argument and the second argument is the usecase
>>> +			id of the client.
>>> +For Example:
>>> +	venus {
>>> +		cache-slice-names = "vidsc0", "vidsc1";
>>> +	 	cache-slices = <&llcc VIDSC0_ID>, <&llcc VIDSC1_ID>;
>>> +	};
>>> --
>>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora 
>>> Forum,
>>> a Linux Foundation Collaborative Project
>>> 
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