Subject: [PATCH 06/12] omap: mailbox: Flush posted write when acking mailbox irq

From: [email-masked] (Tony Lindgren)
Date: Fri, 25 Sep 2009 08:51:22 -0700

* Artem Bityutskiy <[email-masked]> [090925 00:15]:
> On 09/25/2009 02:39 AM, Tony Lindgren wrote:
>> From: Hiroshi DOYU<[email-masked]>
>>
>> The only way to flush posted write to L4 bus is to do a read back
>> of the same register right after the write.
>
> Just curious, is it really necessary to read back the _same_ register?
> Would reading back any L4 bus-related register be sufficient?

It seems that reading back any register in the same device will do it.

Tony