From: greg@kroah•com (Greg KH)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH] usb: ehci: make HC see up-to-date qh/qtd descriptor ASAP
Date: Tue, 30 Aug 2011 10:48:59 -0700 [thread overview]
Message-ID: <20110830174859.GA23098@kroah.com> (raw)
In-Reply-To: <20110830172642.GE3464@e102144-lin.cambridge.arm.com>
On Tue, Aug 30, 2011 at 06:26:42PM +0100, Will Deacon wrote:
> On Tue, Aug 30, 2011 at 05:38:30PM +0100, Mark Salter wrote:
> > On Wed, 2011-08-31 at 00:03 +0800, ming.lei at canonical.com wrote:
> > > +/*
> > > + * Writing to dma coherent memory on ARM may be delayed via L2
> > > + * writing buffer, so introduce the helper which can flush L2 writing
> > > + * buffer into memory immediately, especially used to flush ehci
> > > + * descriptor to memory.
> > > + * */
> > > +#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
> > > +static inline void ehci_sync_mem()
> > > +{
> > > + mb();
> > > +}
> > > +#else
> > > +static inline void ehci_sync_mem()
> > > +{
> > > +}
> > > +#endif
> > > +
> >
> > I'm wondering if this doesn't really belong in the DMA API for any
> > future architectures that can't avoid prolonged write buffering to DMA
> > coherent memory. IIUC, ARM mitigates this for most drivers by including
> > an implicit write buffer flush in the mmio write routines. This takes
> > care of the drivers which write to a mmio device register after writing
> > something to shared DMA memory. IIUC, this doesn't help ehci because the
> > host controller is polling to see what the cpu writes to the shared
> > memory. Other hardware which polls shared memory like that will likely
> > have the same problem and could use buffer drain helpers as well.
>
> Right. In this case the buffering is happening at L2 which becomes
> noticeable when measuring performance. We also buffer stores at the
> CPU (regardless of memory type) but because these tend to become visible
> fairly quickly, there isn't a comparable performance problem.
>
> Given that I would expect other architectures to buffer writes at the CPU,
> would it not be worth having an API for flushing to L3 (devices)? It seems
> like this would be a useful addition to the coherent DMA API on platforms
> that handle coherency with non-cacheable memory attributes.
I agree, this seems to be a "new" type of barrier that is needed, as the
code comment above seems to go against what the kernel memory barrier
documentation says about what a memory barrier really does on the
hardware.
greg k-h
next prev parent reply other threads:[~2011-08-30 17:48 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-08-30 16:03 [PATCH] usb: ehci: make HC see up-to-date qh/qtd descriptor ASAP ming.lei at canonical.com
2011-08-30 16:15 ` Alan Stern
2011-08-30 16:38 ` Mark Salter
2011-08-30 17:15 ` Alan Stern
2011-08-30 18:45 ` Mark Salter
2011-08-30 17:26 ` Will Deacon
2011-08-30 17:48 ` Greg KH [this message]
2011-08-30 17:54 ` Will Deacon
2011-08-31 0:23 ` Chen Peter-B29397
2011-08-31 8:49 ` Will Deacon
2011-08-31 12:33 ` Chen Peter-B29397
2011-08-31 13:43 ` Mark Salter
2011-08-31 15:21 ` Will Deacon
2011-08-31 15:27 ` Mark Salter
2011-08-31 16:12 ` Marc Zyngier
2011-08-31 16:55 ` Marc Dietrich
2011-09-01 10:34 ` Marc Zyngier
2011-09-01 11:13 ` Marc Dietich
2011-09-01 19:08 ` Stephen Warren
2011-09-02 9:50 ` Marc Zyngier
2011-09-02 17:07 ` Stephen Warren
2011-09-02 11:13 ` Marc Dietich
2011-08-31 17:46 ` Nicolas Pitre
2011-08-31 17:51 ` Will Deacon
2011-08-31 18:19 ` Rob Herring
2011-08-31 18:35 ` Mark Salter
2011-08-31 18:49 ` Rob Herring
2011-08-31 18:58 ` Mark Salter
2011-08-31 19:35 ` Will Deacon
2011-09-08 22:41 ` Mark Salter
2011-10-31 6:49 ` Pandita, Vikram
2011-08-31 0:56 ` Ming Lei
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