Subject: [RFC PATCH 03/11] ARM: protect usage of cr_alignment by #ifdef CONFIG_CPU_CP15

From: [email-masked] (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 23 Jan 2012 06:43:46 +0100

On 12:13 Sun 22 Jan     , Uwe Kleine-K?nig wrote:
> Signed-off-by: Uwe Kleine-K?nig <[email-masked]>
> ---
>  arch/arm/include/asm/system.h |    2 ++
>  arch/arm/kernel/entry-armv.S  |    4 ++++
>  arch/arm/kernel/head-common.S |    9 +++++++--
>  arch/arm/kernel/setup.c       |    8 ++++++--
>  arch/arm/mm/alignment.c       |    6 ++++++
>  arch/arm/mm/mmu.c             |    8 +++++++-
>  6 files changed, 32 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
> index e4c96cc..de46477 100644
> --- a/arch/arm/include/asm/system.h
> +++ b/arch/arm/include/asm/system.h
> @@ -185,6 +185,7 @@ extern unsigned int user_debug;
>  #define set_mb(var, value)	do { var = value; smp_mb(); } while (0)
>  #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
>  
> +#ifdef CONFIG_CPU_CP15
>  extern unsigned long cr_no_alignment;	/* defined in entry-armv.S */
>  extern unsigned long cr_alignment;	/* defined in entry-armv.S */
>  
> @@ -224,6 +225,7 @@ static inline void set_copro_access(unsigned int val)
>  	  : : "r" (val) : "cc");
>  	isb();
>  }
> +#endif
>  
>  /*
>   * switch_mm() may do a full cache flush over the context switch,
> diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
> index 3a456c6..15bfeff 100644
> --- a/arch/arm/kernel/entry-armv.S
> +++ b/arch/arm/kernel/entry-armv.S
> @@ -314,8 +314,10 @@ __pabt_svc:
>  ENDPROC(__pabt_svc)
>  
>  	.align	5
> +#ifdef CONFIG_CPU_CP15
>  .LCcralign:
>  	.word	cr_alignment
> +#endif
>  #ifdef MULTI_DABORT
>  .LCprocfns:
>  	.word	processor
> @@ -1146,12 +1148,14 @@ __vectors_end:
>  
>  	.data
>  
> +#ifdef CONFIG_CPU_CP15
>  	.globl	cr_alignment
>  	.globl	cr_no_alignment
>  cr_alignment:
>  	.space	4
>  cr_no_alignment:
>  	.space	4
> +#endif
>  
>  #ifdef CONFIG_MULTI_IRQ_HANDLER
>  	.globl	handle_arch_irq
> diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
> index 854bd22..2f560c5 100644
> --- a/arch/arm/kernel/head-common.S
> +++ b/arch/arm/kernel/head-common.S
> @@ -98,8 +98,9 @@ __mmap_switched:
>  	str	r9, [r4]			@ Save processor ID
>  	str	r1, [r5]			@ Save machine type
>  	str	r2, [r6]			@ Save atags pointer
> -	bic	r4, r0, #CR_A			@ Clear 'A' bit
> -	stmia	r7, {r0, r4}			@ Save control register values
> +	cmp	r7, #0
> +	bicne	r4, r0, #CR_A			@ Clear 'A' bit
> +	stmneia	r7, {r0, r4}			@ Save control register values
>  	b	start_kernel
>  ENDPROC(__mmap_switched)
>  
> @@ -113,7 +114,11 @@ __mmap_switched_data:
>  	.long	processor_id			@ r4
>  	.long	__machine_arch_type		@ r5
>  	.long	__atags_pointer			@ r6
> +#ifdef CONFIG_CPU_CP15
>  	.long	cr_alignment			@ r7
> +#else
> +	.long	0
> +#endif
>  	.long	init_thread_union + THREAD_START_SP @ sp
>  	.size	__mmap_switched_data, . - __mmap_switched_data
>  
> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> index 129fbd5..3849737 100644
> --- a/arch/arm/kernel/setup.c
> +++ b/arch/arm/kernel/setup.c
> @@ -459,9 +459,13 @@ static void __init setup_processor(void)
>  	cpu_cache = *list->cache;
>  #endif
>  
> -	printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
> +	printk("CPU: %s [%08x] revision %d (ARMv%s)",
>  	       cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
> -	       proc_arch[cpu_architecture()], cr_alignment);
> +	       proc_arch[cpu_architecture()]);
> +
> +#ifdef CONFIG_CPU_CP15
> +	printk(KERN_CONT ", cr=%08lx\n", cr_alignment);
> +#endif
>  
>  	snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c",
>  		 list->arch_name, ENDIANNESS);
> diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
> index caf14dc..119d178 100644
> --- a/arch/arm/mm/alignment.c
> +++ b/arch/arm/mm/alignment.c
> @@ -89,7 +89,11 @@ core_param(alignment, ai_usermode, int, 0600);
>  /* Return true if and only if the ARMv6 unaligned access model is in use. */
>  static bool cpu_is_v6_unaligned(void)
>  {
> +#ifdef CONFIG_CPU_CP15
>  	return cpu_architecture() >= CPU_ARCH_ARMv6 && (cr_alignment & CR_U);
> +#else
> +	return 0;
> +#endif
>  }
>  
>  static int safe_usermode(int new_usermode, bool warn)
> @@ -961,12 +965,14 @@ static int __init alignment_init(void)
>  		return -ENOMEM;
>  #endif
>  
> +#ifdef CONFIG_CPU_CP15
>  	if (cpu_is_v6_unaligned()) {
>  		cr_alignment &= ~CR_A;
>  		cr_no_alignment &= ~CR_A;
>  		set_cr(cr_alignment);
>  		ai_usermode = safe_usermode(ai_usermode, false);
>  	}
> +#endif
why if CPU_CP15 is not supported cpu_is_v6_unaligned return 0
>  
>  	hook_fault_code(FAULT_CODE_ALIGNMENT, do_alignment, SIGBUS, BUS_ADRALN,
>  			"alignment exception");
> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> index 94c5a0c..f6dbe1a 100644
> --- a/arch/arm/mm/mmu.c
> +++ b/arch/arm/mm/mmu.c
> @@ -109,8 +109,10 @@ static int __init early_cachepolicy(char *p)
>  
>  		if (memcmp(p, cache_policies[i].policy, len) == 0) {
>  			cachepolicy = i;
> +#ifdef CONFIG_CPU_CP15
can you use if (IS_ENABLED(x)) instead

Best Regards,
J.