Subject: [PATCH 06/10 V2] spi: Add SPI driver for mx233/mx28

From: [email-masked] (Marek Vasut)
Date: Fri, 3 Aug 2012 16:00:43 +0200

Dear Fabio Estevam,

> On Fri, Aug 3, 2012 at 10:38 AM, Thomas Petazzoni
> 
> <[email-masked]> wrote:
> > It sounds really strange to manipulate WAIT_FOR_CMD and WAIT_FOR_IRQ
> > bits to adjust the chip select, and when reading the driver, it seemed
> > suspicious to me. After going through the datasheet, indeed those bits
> > are the appropriate one to select between the SS0, SS1 and SS2 chip
> > selects, but I find the code not really obvious. Would it be possible
> > to make it more obvious either by adding or comment or doing something
> > like:
> > 
> > /* Should be put in some header file */
> > #define BM_SSP_CTRL0_SPI_CS_BITS (20)
> > 
> > +static void mxs_spi_set_cs(struct mxs_spi *spi, unsigned cs)
> > +{
> > +       struct mxs_ssp *ssp = &spi->ssp;
> > +
> > +       writel(0x3 << BM_SSP_CTRL0_SPI_CS_BITS,
> > +              ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
> > +       writel(cs,
> > +              ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
> > +}
> 
> I agree with Thomas.
> 
> In U-boot I did the following in order to be able to select the
> different chip selects:
> http://git.denx.de/?p=u-boot.git;a=commitdiff;h=148ca64f327a89ef77e84756f5d
> 351af33e59b64

I'll just add the following comment if it's ok with you:

/*
 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
 *
 * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
 * in HW_SSP_CTRL0 register do have multiple usage, please refer to
 * the datasheet for further details. In SPI mode, they are used to
 * toggle the chip-select lines (nCS pins).
 */

I hope it'll suffice. Recycling bits in registers is really crazy practice and 
I'd like to avoid these getting out of scope of this flaw's location.

> Thanks,
> Fabio Estevam

Best regards,
Marek Vasut