Subject: [RFC v1] PCIe support for the Armada 370 and Armada XP SoCs

From: [email-masked] (Jason Gunthorpe)
Date: Thu, 13 Dec 2012 13:47:18 -0700

On Thu, Dec 13, 2012 at 09:42:29PM +0100, Thierry Reding wrote:

> So I tried this today and it breaks horribly. There's some internal
> abort or something. I don't have access to the hardware right now and
> forgot to save the log output, but I can follow up in the morning. Also
> up until the abort, bus 0000:00.0 was identified as the virtual switch
> within the FPGA that's connected to port 0, so that would indicate that
> it isn't in fact compliant and neither root port is reachable via the
> regular mapping.
> 
> I suppose that may be the reason why the downstream code implements the
> special case for accesses to the root ports' configuration space.

With the special case, what does device 0:0.0 show up as? What class?

Jason