Subject: [PATCH V3 3/4] ARM: dts: tegra: Correct PCIe entry

From: [email-masked] (Thierry Reding)
Date: Mon, 10 Jun 2013 21:55:12 +0200

On Wed, Jun 05, 2013 at 12:27:31AM +0530, Jay Agarwal wrote:
[...]
> @@ -29,7 +29,7 @@
>  		ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000   /* port 0 configuration space */
>  			  0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */
>  			  0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */
> -			  0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */
> +			  0x81000000 0 0          0x02000000 0 0x00100000   /* downstream I/O */
>  			  0x82000000 0 0x20000000 0x20000000 0 0x10000000   /* non-prefetchable memory */
>  			  0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */

That increases the I/O region size from 64 KiB to 1 MiB. Why is that
necessary? I/O operations can only address 64 KiB, so I don't think
adding more makes any sense.

Thierry
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