Subject: [PATCH RFC 3/8] clk: sunxi: add gating support to PLL1

From: [email-masked] (Maxime Ripard)
Date: Tue, 23 Jul 2013 15:15:24 +0200

On Mon, Jul 22, 2013 at 10:01:07PM -0300, Emilio L?pez wrote:
> This commit adds gating support to PLL1 on the clock driver. This makes
> the PLL1 implementation fully compatible with PLL4 as well.
> 
> Signed-off-by: Emilio L?pez <[email-masked]>

Acked-by: Maxime Ripard <[email-masked]>

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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