Subject: [PATCH v1 04/14] clk: Add set_rate_and_parent() op

From: [email-masked] (Stephen Boyd)
Date: Thu, 25 Jul 2013 09:45:42 -0700

On 07/25, Tomasz Figa wrote:
> On Wednesday 24 of July 2013 17:43:32 Stephen Boyd wrote:
> > Some of Qualcomm's clocks can change their parent and rate at the
> > same time with a single register write. Add support for this
> > hardware to the common clock framework by adding a new
> > set_rate_and_parent() op. When the clock framework determines
> > that both the parent and the rate are going to change during
> > clk_set_rate() it will call the .set_rate_and_parent() op if
> > available and fall back to calling .set_parent() followed by
> > .set_rate() otherwise.
> 
> This is strange. Does you hardware support switching parent and rate 
> separately or you always need to set both and so all the fuss here?

It supports setting the parent or setting the rate, or setting
both at the same time.

> 
> If the latter is the case, then maybe you can simply keep parent index and 
> rate cached inside driver data of your clock driver and use them on any 
> .set_rate() or .set_parent() calls?

This will not work. In fact, doing that would cause us to
overclock hardware for a short time between switching the parent
and the rate.

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