Subject: [linux-sunxi] [PATCH 0/4] Add support for the Allwinner A31 Reset Controllers

From: [email-masked] (Maxime Ripard)
Date: Sun, 6 Oct 2013 10:29:17 +0200

Hi Roman,

On Sun, Oct 06, 2013 at 01:32:13AM +0200, Arokux X wrote:
> On Sat, Oct 5, 2013 at 4:39 PM, Maxime Ripard
> <[email-masked]> wrote:
> > Hi everyone,
> >
> > This patchset adds support for the reset controllers found in the Allwinner A31
> > SoCs. Since these controllers are pretty simple, basically just a few MMIO
> > registers, with a single bit controlling the reset state of the other devices
> > it asserts in reset, the driver is quite simple as well.
> 
> I think we need something smarter here. There are reset bits all over
> the place. After a hint by Emilio and small chat with Oliver I've
> realized I have 3 reset bits in USB host clock module [0].

I wasn't aware there were other IPs behaving like this in older SoCs.
Thanks for pointing this out.

Something smarter in what sense? It's just one bit to put in one
register, I don't really see how it can be "smart".

> Maybe implementation like this one [1] where a mask can be passed as a
> parameter will be more appropriate? (Those reset bits behave the same
> as gatable clocks really.)

No, they don't behave like gatable clocks, and they shouldn't be
implemented with the clock framework. Whenever you disable a clock, the
child device will retain its configuration, while with the reset part,
well, it will just be reset. This makes one huge difference.

We have a shiny new reset framework for this, made exactly for these
cases, why not use it?

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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