From: catalin.marinas@arm•com (Catalin Marinas)
To: linux-arm-kernel@lists•infradead.org
Subject: [RFC PATCH] arm64: KVM: honor cacheability attributes on S2 page fault
Date: Thu, 10 Oct 2013 12:24:26 +0100 [thread overview]
Message-ID: <20131010112425.GB21380@arm.com> (raw)
In-Reply-To: <525667DB.7090705@arm.com>
On Thu, Oct 10, 2013 at 09:39:55AM +0100, Marc Zyngier wrote:
> On 10/10/13 05:51, Anup Patel wrote:
> > Are you planning to go ahead with this approach ?
>
> [adding Catalin, as we heavily discussed this recently]
>
> Not as such, as it doesn't solve the full issue. It merely papers over
> the whole "my cache is off" problem. More specifically, any kind of
> speculative access from another CPU while caches are off in the guest
> completely nukes the benefit of this patch.
>
> Also, turning the the caches off is another source of problems, as
> speculation also screws up set/way invalidation.
Indeed. The set/way operations trapping and broadcasting (or deferring)
to other CPUs in software just happens to work but there is no
guarantee, sooner or later we'll hit a problem. I'm even tempted to
remove flush_dcache_all() calls on the booting path for the arm64
kernel, we already require that whatever runs before Linux should
clean&invalidate the caches.
Basically, with KVM a VCPU even if running with caches/MMU disabled can
still get speculative allocation into the cache. The reason for this is
the other cacheable memory aliases created by the host kernel and
qemu/kvmtool. I can't tell whether Xen has this issue but it may be
easier in Xen to avoid memory aliases.
> > We really need this patch for X-Gene L3 cache.
>
> So far, I can see two possibilities:
> - either we mandate caches to be always on (DC bit, and you're not
> allowed to turn the caches off).
That's my preferred approach. For hotplug, idle, the guest would use an
HVC call (PSCI) and the host takes care of re-enabling the DC bit. But
we may not catch all cases (kexec probably).
> - Or we mandate that caches are invalidated (by VA) for each write that
> is performed with caches off.
For some things like run-time code patching, on ARMv8 we need to do at
least I-cache maintenance since the CPU can allocate into the I-cache
(even if there are no aliases).
--
Catalin
next prev parent reply other threads:[~2013-10-10 11:24 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-10 9:51 [RFC PATCH] arm64: KVM: honor cacheability attributes on S2 page fault Marc Zyngier
2013-09-11 12:21 ` Anup Patel
2013-09-11 12:35 ` Marc Zyngier
2013-09-11 19:38 ` Christoffer Dall
2013-10-10 4:51 ` Anup Patel
2013-10-10 8:39 ` Marc Zyngier
2013-10-10 11:24 ` Catalin Marinas [this message]
2013-10-10 16:09 ` Anup Patel
2013-10-11 12:38 ` Catalin Marinas
2013-10-11 14:27 ` Anup Patel
2013-10-11 14:37 ` Catalin Marinas
2013-10-11 14:50 ` Anup Patel
2013-10-11 14:59 ` Marc Zyngier
2013-10-11 15:32 ` Anup Patel
2013-10-11 15:44 ` Catalin Marinas
2013-10-12 18:24 ` Anup Patel
2013-10-15 14:38 ` Catalin Marinas
2013-10-17 4:19 ` Anup Patel
2013-10-17 11:16 ` Catalin Marinas
2013-10-19 14:45 ` Christoffer Dall
2013-10-20 9:06 ` Catalin Marinas
2013-09-11 18:06 ` Peter Maydell
2013-09-11 19:25 ` Christoffer Dall
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