From: arnd@arndb•de (Arnd Bergmann)
To: linux-arm-kernel@lists•infradead.org
Subject: [RESEND PATCHv2 1/3] arm: socfpga: Set the SDMMC clock phase in system manager
Date: Tue, 15 Oct 2013 14:50:48 +0200 [thread overview]
Message-ID: <201310151450.48650.arnd@arndb.de> (raw)
In-Reply-To: <1381780051-1826-1-git-send-email-dinguyen@altera.com>
On Monday 14 October 2013, dinguyen at altera.com wrote:
> +void socfpga_sysmgr_set_dwmmc_drvsel_smpsel(u32 drvsel, u32 smplsel)
> +{
> + u32 hs_timing;
> +
> + hs_timing = SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel);
> + writel(hs_timing, sys_manager_base_addr + SYSMGR_SDMMCGRP_CTRL_OFFSET);
> +}
> +EXPORT_SYMBOL(socfpga_sysmgr_set_dwmmc_drvsel_smpsel);
This looks like the wrong approach. What are you trying to do? If you want to
set a clock, please use the clk API.
Arnd
next prev parent reply other threads:[~2013-10-15 12:50 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-10-14 19:47 [RESEND PATCHv2 1/3] arm: socfpga: Set the SDMMC clock phase in system manager dinguyen at altera.com
2013-10-14 19:47 ` [RESEND PATCHv2 2/3] mmc: dw_mmc-socfpga: Clean up SOCFPGA platform specific functionality dinguyen at altera.com
2013-10-14 19:47 ` [RESEND PATCHv2 3/3] arm: dts: socfpga: Add support for SD/MMC dinguyen at altera.com
2013-10-15 6:51 ` [RESEND PATCHv2 1/3] arm: socfpga: Set the SDMMC clock phase in system manager Jaehoon Chung
2013-10-15 12:37 ` Dinh Nguyen
2013-10-15 12:50 ` Arnd Bergmann [this message]
2013-10-15 13:22 ` Dinh Nguyen
2013-10-15 19:01 ` Arnd Bergmann
2013-10-15 19:19 ` Dinh Nguyen
2013-10-15 19:47 ` Arnd Bergmann
2013-10-15 20:21 ` Dinh Nguyen
2013-10-16 18:56 ` Arnd Bergmann
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