From: arnd@arndb•de (Arnd Bergmann)
To: linux-arm-kernel@lists•infradead.org
Subject: [RESEND LIST PATCHv7 1/4] clk: socfpga: Add a clk-phase property to the "altr, socfpga-gate-clk"
Date: Wed, 18 Dec 2013 22:21:46 +0100 [thread overview]
Message-ID: <201312182221.46506.arnd@arndb.de> (raw)
In-Reply-To: <20131218205636.23538.50735@quantum>
On Wednesday 18 December 2013, Mike Turquette wrote:
> > diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> > index f936476..616d9ee 100644
> > --- a/arch/arm/boot/dts/socfpga.dtsi
> > +++ b/arch/arm/boot/dts/socfpga.dtsi
> > @@ -413,6 +413,7 @@
> > compatible = "altr,socfpga-gate-clk";
> > clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
> > clk-gate = <0xa0 8>;
> > + clk-phase = <0 3>;
>
> Looking at this again, I have a hard time understanding the values in
> the clk-phase property. You reference some functions in the property
> definition above, but they are not obvious to me.
>
> Additionally I wonder if the binding would better if the clock-phase
> property was simply the value in degrees. E.g:
>
> clk-phase = <315>; // 315 degrees
I would definitely prefer using degrees over an arbitrary enumeration that
might work on some platforms but not on others.
I'm also a bit skeptical about the idea of putting the phase into the clock
provider rather than the consumer, given the comments about the
clk_set_phase() interface earlier. Generally we try to avoid having
consumer-specific settings in a provider node (for any DT binding,
not just clocks). Can't you have the same numbers in the dw-mshc
node instead and let the mmc driver call clk_set_phase instead?
If every clock has a fixed phase for a given piece of hardware, it
could even be set automatically by making the common clk code read
the clk-phase attribute at the time a driver calls clk_get.
Arnd
next prev parent reply other threads:[~2013-12-18 21:21 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-16 17:04 [RESEND LIST PATCHv7 0/4] socfpga: Enable SD/MMC support dinguyen at altera.com
2013-12-16 17:04 ` [RESEND LIST PATCHv7 1/4] clk: socfpga: Add a clk-phase property to the "altr, socfpga-gate-clk" dinguyen at altera.com
2013-12-17 7:46 ` [RESEND LIST PATCHv7 1/4] clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk" zhangfei
2013-12-17 13:44 ` Dinh Nguyen
2013-12-17 14:47 ` zhangfei
2013-12-17 23:55 ` [RESEND LIST PATCHv7 1/4] clk: socfpga: Add a clk-phase property to the "altr, socfpga-gate-clk" Mike Turquette
2013-12-18 4:06 ` Dinh Nguyen
2013-12-18 20:56 ` Mike Turquette
2013-12-18 21:21 ` Arnd Bergmann [this message]
2013-12-19 4:04 ` Dinh Nguyen
2013-12-19 5:50 ` Arnd Bergmann
2013-12-16 17:04 ` [RESEND LIST PATCHv7 2/4] dts: socfpga: Add support for SD/MMC on the SOCFPGA platform dinguyen at altera.com
2013-12-16 17:04 ` [RESEND LIST PATCHv7 3/4] mmc: dw_mmc-socfpga: Remove the SOCFPGA specific platform for dw_mmc dinguyen at altera.com
2013-12-16 17:04 ` [RESEND LIST PATCHv7 4/4] ARM: socfpga_defconfig: enable SD/MMC support dinguyen at altera.com
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