Subject: [Q] L1_CACHE_BYTES on flush_pfn_alias function.

From: [email-masked] (Catalin Marinas)
Date: Mon, 27 Jan 2014 16:43:37 +0000

Please do not top-post.

On Sun, Jan 26, 2014 at 05:13:43AM +0000, Jungseung Lee wrote:
> Not to flush some more bytes. In the scenario, they can *omit* to flush last 32 bytes.
> 
> L1_CACHE_BYTES = 64 (ARM v7, CA9)
> 
> asm(    "mcrr   p15, 0, %1, %0, c14\n"
>     "   mcr p15, 0, %2, c7, c10, 4"
>         :
>         : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero)
>         : "cc");

Ah, I got it now. I think this should be (to + PAGE_SIZE - 1). My
reading of the ARM ARM is that the bottom bits of the address are
ignored by mcrr.

-- 
Catalin