From: catalin.marinas@arm•com (Catalin Marinas)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH 3/6] irqchip: gic: use writel instead of dsb + writel_relaxed
Date: Fri, 14 Feb 2014 16:48:03 +0000 [thread overview]
Message-ID: <20140214164803.GG10590@arm.com> (raw)
In-Reply-To: <20140214163039.GG21986@mudshark.cambridge.arm.com>
On Fri, Feb 14, 2014 at 04:30:39PM +0000, Will Deacon wrote:
> Well, the results are in (*drum roll*)...
>
> On Fri, Feb 07, 2014 at 11:23:37AM +0000, Will Deacon wrote:
> > On Thu, Feb 06, 2014 at 03:20:48PM +0000, Catalin Marinas wrote:
> > > On Thu, Feb 06, 2014 at 01:26:44PM +0000, Will Deacon wrote:
> > > > Ok, my reasoning is as follows:
> > > >
> > > > - CPU0 tries to message CPU1. It writes to a location in normal memory,
> > > > then writes to the GICD to send the SGI
> > > >
> > > > - We need to ensure that CPU1 observes the write to normal memory before
> > > > the write to GICD reaches the distributor. This is *not* about end-point
> > > > ordering (the usual non-coherent DMA example).
> > > >
> > > > - A dmb ishst ensures that the two writes are observed in order by CPU1
> > > > (and, in fact, the inner-shareable domain containing CPU0).
> > >
> > > The last bullet point is not correct. DMB would only guarantee that the
> > > two writes (memory and GICD) are observed by CPU1 if CPU1 actually read
> > > the GICD (observability is defined for master accesses).
> >
> > Rather than attempt to solve this via email (your examples below are already
> > getting hard to follow :), how about we sit down with $drink_of_choice and
> > post back here with our conclusions?
>
> ... and it turns out that a dmb(ishst) is sufficient!
Until we hear otherwise ;)
--
Catalin
next prev parent reply other threads:[~2014-02-14 16:48 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-06 11:30 [PATCH 1/6] arm64: barriers: allow dsb macro to take option parameter Will Deacon
2014-02-06 11:30 ` [PATCH 2/6] arm64: barriers: make use of barrier options with explicit barriers Will Deacon
2014-02-06 11:41 ` Catalin Marinas
2014-02-06 11:45 ` Will Deacon
2014-02-06 11:49 ` Catalin Marinas
2014-02-06 11:52 ` Will Deacon
2014-02-06 11:30 ` [PATCH 3/6] irqchip: gic: use writel instead of dsb + writel_relaxed Will Deacon
2014-02-06 11:39 ` Marc Zyngier
2014-02-06 11:45 ` Catalin Marinas
2014-02-06 11:51 ` Will Deacon
2014-02-06 11:54 ` Catalin Marinas
2014-02-06 11:57 ` Will Deacon
2014-02-06 12:00 ` Catalin Marinas
2014-02-06 12:13 ` Will Deacon
2014-02-06 12:23 ` Catalin Marinas
2014-02-06 13:26 ` Will Deacon
2014-02-06 15:20 ` Catalin Marinas
2014-02-07 11:23 ` Will Deacon
2014-02-07 12:57 ` Catalin Marinas
2014-02-14 16:30 ` Will Deacon
2014-02-14 16:48 ` Catalin Marinas [this message]
2014-02-14 17:18 ` Rob Herring
2014-02-06 11:30 ` [PATCH 4/6] iommu/arm-smmu: provide option to dsb macro when publishing tables Will Deacon
2014-02-06 11:51 ` Catalin Marinas
2014-02-06 11:30 ` [PATCH 5/6] arm64: barriers: wire up new barrier options Will Deacon
2014-02-06 11:55 ` Catalin Marinas
2014-02-06 11:30 ` [PATCH 6/6] arm64: barriers: use barrier() instead of smp_mb() when !SMP Will Deacon
2014-02-06 11:56 ` Catalin Marinas
2014-02-06 11:39 ` [PATCH 1/6] arm64: barriers: allow dsb macro to take option parameter Catalin Marinas
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20140214164803.GG10590@arm.com \
--to=catalin.marinas@arm$(echo .)com \
--cc=linux-arm-kernel@lists$(echo .)infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox