Subject: [RFC PATCH 3/6] PM / Voltagedomain: introduce voltage domain driver support

From: [email-masked] (Mike Turquette)
Date: Wed, 19 Mar 2014 15:35:36 -0700

Quoting Nishanth Menon (2014-03-10 12:25:43)
> On 03/10/2014 01:01 PM, Mark Brown wrote:
> > On Mon, Mar 10, 2014 at 12:41:05PM -0500, Nishanth Menon wrote:
> > 
> >> The only other options are:
> >> a) Abstract it at a higher level at "user drivers", since they are
> >> aware of the sequencing needs - but this partially defeats the
> >> purpose, unless ofcourse, we do a tricky implementation such as:
> >> clk a, b, c -> prenotifiers in a, postnotifiers in c (which as you
> >> mentioned is a little trickier to get right).
> >> b) introduce a higher level generic dvfs function[1] which does not
> >> seem very attractive either.

I disagree that a higher level DVFS interface is unattractive. I think
it has taken a while to get there but people are finally interested in
this. A small amount of discussion about this took place at Linaro
Connect earlier this month (just hallway talk) but we shouldn't rule out
the idea of a general framework for managing DVFS, which frankly is
complex enough to merit not being shoved into the clock layer.

> > 
> >> Any other suggestions other than limiting the usage(and documenting it
> >> so) and hoping for a future evolution to take this into consideration?
> > 
> > Something might be doable with telling the clock API about maintianing
> > ratios between clocks?  I do think we should have an idea where we'd go
> > with such requirements, even if we don't currently handle it, so that we
> > can hopefully avoid another round of refactoring everything but it
> > doesn't seem 100% essential, just very nice to have.

This sounds reasonable but I must point out that the clock framework
today (based on the existing clk.h api) does not have a single instance
of constraint-based logic. For instance there is no clk_set_min_rate or
clk_set_max_rate or clk_set_rate_range. These have been discussed before
but I feel that pushing something before now would have been premature
given that the level of discussion around those features never hit
critical mass.

So the ratio thing is sensible, but it would be the first
constraint-like mechanism in the clock framework so what that looks like
bares careful consideration.

> > 
> Mike,
> Any suggestions about the above? could we use composite clocks in some
> manner here(even though I think the original intent of the same was
> not the same)?

NACK. Let's just model the hardware in the clock framework, please. If
you need to invent fake clocks to represent other constructs then it
means the framework is missing something (or we're missing an entire
framework, e.g. DVFS).

Regards,
Mike

> -- 
> Regards,
> Nishanth Menon