From: catalin.marinas@arm•com (Catalin Marinas)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH 2/3] ARM: mm: add support for HW coherent systems in PL310
Date: Wed, 9 Apr 2014 15:06:25 +0100 [thread overview]
Message-ID: <20140409140625.GI13737@arm.com> (raw)
In-Reply-To: <20140408201212.067d526d@skate>
On Tue, Apr 08, 2014 at 07:12:12PM +0100, Thomas Petazzoni wrote:
> On Tue, 8 Apr 2014 18:24:25 +0100, Catalin Marinas wrote:
>
> > > of_init = true;
> > > memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));
> > > +
> > > + /*
> > > + * PL310 doesn't need an outer cache sync operation when the
> > > + * system is operating with hardware coherency enabled, as it
> > > + * is done directly in hardware.
> > > + */
> > > + if (of_device_is_compatible(np, "arm,pl310-cache") && is_coherent)
> > > + outer_cache.sync = NULL;
> > > +
> >
> > For this particular case, you can add a specific l2x0_of_data structure
> > with the right compatible string for your platform where
> > outer_cache.sync is NULL,
>
> In fact, I'm not sure using a separate compatible string is possible,
> because there are situations where the hardware platform may be I/O
> coherent, and some situations where it is not the case. For example, in
> the current kernel, the platform is I/O coherent when CONFIG_SMP is
> enabled, but not I/O coherent when CONFIG_SMP is disabled. And it's the
> same hardware platform, so same Device Tree in both cases.
I think Russell has a better solution in his L2 cache cleanup series.
Patch 18/44 introduces a .fixup function which takes the outer_cache_fns
pointer and that's a place where your code can check whether coherency
is present or not (and turn .sync into NULL).
--
Catalin
next prev parent reply other threads:[~2014-04-09 14:06 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-24 16:17 [PATCH 0/3] ARM: implement workaround for Cortex-A9/PL310/PCIe deadlock Thomas Petazzoni
2014-03-24 16:17 ` [PATCH 1/3] ARM: mm: allow sub-architectures to override PCI I/O memory type Thomas Petazzoni
2014-03-24 16:17 ` [PATCH 2/3] ARM: mm: add support for HW coherent systems in PL310 Thomas Petazzoni
2014-04-08 17:24 ` Catalin Marinas
2014-04-08 18:12 ` Thomas Petazzoni
2014-04-09 11:15 ` Catalin Marinas
2014-04-09 14:06 ` Catalin Marinas [this message]
2014-05-06 10:07 ` Thomas Petazzoni
2014-03-24 16:17 ` [PATCH 3/3] ARM: mvebu: implement L2/PCIe deadlock workaround Thomas Petazzoni
2014-04-03 14:07 ` [PATCH 0/3] ARM: implement workaround for Cortex-A9/PL310/PCIe deadlock Thomas Petazzoni
2014-04-03 14:15 ` Russell King - ARM Linux
2014-04-07 9:10 ` Thomas Petazzoni
2014-04-07 12:13 ` Catalin Marinas
2014-04-14 16:59 ` Will Deacon
2014-04-14 18:39 ` Thomas Petazzoni
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