From: catalin.marinas@arm•com (Catalin Marinas)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH resend 04/15] arm64: add support for kernel mode NEON in interrupt context
Date: Tue, 6 May 2014 17:49:19 +0100 [thread overview]
Message-ID: <20140506164918.GK23957@arm.com> (raw)
In-Reply-To: <1398959381-8126-5-git-send-email-ard.biesheuvel@linaro.org>
On Thu, May 01, 2014 at 04:49:36PM +0100, Ard Biesheuvel wrote:
> diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h
> index 7a900142dbc8..05e1b24aca4c 100644
> --- a/arch/arm64/include/asm/fpsimd.h
> +++ b/arch/arm64/include/asm/fpsimd.h
> @@ -41,6 +41,17 @@ struct fpsimd_state {
> unsigned int cpu;
> };
>
> +/*
> + * Struct for stacking the bottom 'n' FP/SIMD registers.
> + */
> +struct fpsimd_partial_state {
> + u32 num_regs;
> + u32 fpsr;
> + u32 fpcr;
> + __uint128_t vregs[32] __aligned(16);
> +} __aligned(16);
Do we need this explicit alignment here?
> diff --git a/arch/arm64/include/asm/fpsimdmacros.h b/arch/arm64/include/asm/fpsimdmacros.h
> index bbec599c96bd..69e75134689d 100644
> --- a/arch/arm64/include/asm/fpsimdmacros.h
> +++ b/arch/arm64/include/asm/fpsimdmacros.h
> @@ -62,3 +62,38 @@
> ldr w\tmpnr, [\state, #16 * 2 + 4]
> msr fpcr, x\tmpnr
> .endm
> +
> +.altmacro
> +.macro fpsimd_save_partial state, numnr, tmpnr1, tmpnr2
> + mrs x\tmpnr1, fpsr
> + str w\numnr, [\state]
> + mrs x\tmpnr2, fpcr
> + stp w\tmpnr1, w\tmpnr2, [\state, #4]
> + adr x\tmpnr1, 0f
> + add \state, \state, x\numnr, lsl #4
> + sub x\tmpnr1, x\tmpnr1, x\numnr, lsl #1
> + br x\tmpnr1
> + .irp qa, 30, 28, 26, 24, 22, 20, 18, 16, 14, 12, 10, 8, 6, 4, 2, 0
> + .irp qb, %(qa + 1)
> + stp q\qa, q\qb, [\state, # -16 * \qa - 16]
> + .endr
> + .endr
> +0:
> +.endm
> +
> +.macro fpsimd_restore_partial state, tmpnr1, tmpnr2
> + ldp w\tmpnr1, w\tmpnr2, [\state, #4]
> + msr fpsr, x\tmpnr1
> + msr fpcr, x\tmpnr2
> + adr x\tmpnr1, 0f
> + ldr w\tmpnr2, [\state]
> + add \state, \state, x\tmpnr2, lsl #4
> + sub x\tmpnr1, x\tmpnr1, x\tmpnr2, lsl #1
> + br x\tmpnr1
> + .irp qa, 30, 28, 26, 24, 22, 20, 18, 16, 14, 12, 10, 8, 6, 4, 2, 0
> + .irp qb, %(qa + 1)
> + ldp q\qa, q\qb, [\state, # -16 * \qa - 16]
> + .endr
> + .endr
> +0:
> +.endm
BTW, it may be better if num_regs is placed at the end of the structure,
especially since you use stp to store both fpsr and fpcr (though I
haven't rewritten the above to see how they look).
--
Catalin
next prev parent reply other threads:[~2014-05-06 16:49 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-01 15:49 [PATCH resend 00/15] arm64 crypto roundup Ard Biesheuvel
2014-05-01 15:49 ` [PATCH resend 01/15] asm-generic: allow generic unaligned access if the arch supports it Ard Biesheuvel
2014-05-06 14:31 ` Catalin Marinas
2014-05-06 14:34 ` Ard Biesheuvel
2014-05-06 15:14 ` Catalin Marinas
2014-05-01 15:49 ` [PATCH resend 02/15] arm64: add abstractions for FPSIMD state manipulation Ard Biesheuvel
2014-05-06 14:43 ` Catalin Marinas
2014-05-06 14:48 ` Ard Biesheuvel
2014-05-06 15:12 ` Catalin Marinas
2014-05-06 15:42 ` Catalin Marinas
2014-05-01 15:49 ` [PATCH resend 03/15] arm64: defer reloading a task's FPSIMD state to userland resume Ard Biesheuvel
2014-05-06 16:08 ` Catalin Marinas
2014-05-06 16:25 ` Ard Biesheuvel
2014-05-06 16:31 ` Catalin Marinas
2014-05-01 15:49 ` [PATCH resend 04/15] arm64: add support for kernel mode NEON in interrupt context Ard Biesheuvel
2014-05-06 16:49 ` Catalin Marinas [this message]
2014-05-06 17:09 ` Ard Biesheuvel
2014-05-01 15:49 ` [PATCH resend 05/15] arm64/crypto: SHA-1 using ARMv8 Crypto Extensions Ard Biesheuvel
2014-05-01 15:49 ` [PATCH resend 06/15] arm64/crypto: SHA-224/SHA-256 " Ard Biesheuvel
2014-05-01 15:49 ` [PATCH resend 07/15] arm64/crypto: GHASH secure hash " Ard Biesheuvel
2014-05-01 15:49 ` [PATCH resend 08/15] arm64/crypto: AES " Ard Biesheuvel
2014-05-01 15:49 ` [PATCH resend 09/15] arm64/crypto: AES in CCM mode " Ard Biesheuvel
2014-05-07 14:45 ` [PATCH resend 00/15] arm64 crypto roundup Catalin Marinas
2014-05-07 19:58 ` Ard Biesheuvel
2014-05-08 11:22 ` Ard Biesheuvel
2014-05-08 21:50 ` Catalin Marinas
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