From: will.deacon@arm•com (Will Deacon)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH v3 02/10] devicetree: Add generic IOMMU device tree bindings
Date: Fri, 27 Jun 2014 14:55:38 +0100 [thread overview]
Message-ID: <20140627135537.GU26276@arm.com> (raw)
In-Reply-To: <1403815790-8548-3-git-send-email-thierry.reding@gmail.com>
Hi Thierry,
On Thu, Jun 26, 2014 at 09:49:42PM +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia•com>
>
> This commit introduces a generic device tree binding for IOMMU devices.
> Only a very minimal subset is described here, but it is enough to cover
> the requirements of both the Exynos System MMU and Tegra SMMU as
> discussed here:
>
> https://lkml.org/lkml/2014/4/27/346
>
> Signed-off-by: Thierry Reding <treding@nvidia•com>
[...]
> +Required properties:
> +--------------------
> +- #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
> + address.
> +
> +Typical values for the above include:
> +- #iommu-cells = <0>: Single master IOMMU devices are not configurable and
> + therefore no additional information needs to be encoded in the specifier.
> + This may also apply to multiple master IOMMU devices that do not allow the
> + association of masters to be configured.
A multiple-master capable IOMMU could be built with a single master, but
we'd still need #iommu-cells > 0 here. I appreciate this is just an example,
but the wording sounds like it's enforced.
> +- #iommu-cells = <1>: Multiple master IOMMU devices may need to be configured
> + in order to enable translation for a given master. In such cases the single
> + address cell corresponds to the master device's ID.
Again, we will definitely need more than one cell in this case, as I fully
expect multiple StreamIDs for each master (e.g. Qualcomm mentioned on the
list the other day that they have a master emitting 43 unique IDs).
Anyway, the actual binding looks great, I just don't want people to think
they need to do something different because they don't fit your example
use-cases.
> +Multiple-master IOMMU:
> +----------------------
> +
> + iommu {
> + /* the specifier represents the ID of the master */
> + #iommu-cells = <1>;
> + };
> +
> + master {
> + /* device has master ID 42 in the IOMMU */
> + iommus = <&/iommu 42>;
> + };
> +
> +Multiple-master IOMMU with configurable DMA window:
> +---------------------------------------------------
> +
> + / {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + iommu {
> + /* master ID, address and length of DMA window */
> + #iommu-cells = <4>;
> + };
> +
> + master {
> + /* master ID 42, 4 GiB DMA window starting at 0 */
> + iommus = <&/iommu 42 0 0x1 0x0>;
> + };
> + };
Could you also please include an example of a master with multiple IDs?
Will
next prev parent reply other threads:[~2014-06-27 13:55 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-26 20:49 [RFC 00/10] Add NVIDIA Tegra124 IOMMU support Thierry Reding
2014-06-26 20:49 ` [RFC 01/10] iommu: Add IOMMU device registry Thierry Reding
2014-06-27 6:58 ` Thierry Reding
2014-07-03 10:37 ` Varun Sethi
2014-07-04 11:05 ` Joerg Roedel
2014-07-04 13:47 ` Thierry Reding
2014-07-04 13:49 ` Will Deacon
2014-07-06 18:17 ` Arnd Bergmann
2014-07-07 11:42 ` Thierry Reding
2014-06-26 20:49 ` [PATCH v3 02/10] devicetree: Add generic IOMMU device tree bindings Thierry Reding
2014-06-27 13:55 ` Will Deacon [this message]
2014-06-30 22:24 ` Stephen Warren
2014-07-04 6:42 ` Varun Sethi
2014-07-04 9:05 ` Arnd Bergmann
2014-06-26 20:49 ` [RFC 03/10] of: Add NVIDIA Tegra124 memory controller binding Thierry Reding
2014-06-26 20:49 ` [RFC 04/10] memory: Add Tegra124 memory controller support Thierry Reding
2014-06-27 7:41 ` Joseph Lo
2014-06-27 8:17 ` Thierry Reding
2014-06-27 8:24 ` Hiroshi Doyu
2014-06-27 9:46 ` Hiroshi DOyu
2014-06-27 11:08 ` Thierry Reding
2014-06-27 21:33 ` Stephen Warren
2014-06-27 11:07 ` Arnd Bergmann
2014-06-27 11:15 ` Thierry Reding
2014-06-27 21:37 ` Stephen Warren
2014-06-27 13:29 ` Mikko Perttunen
2014-06-30 22:43 ` Stephen Warren
2014-07-01 12:14 ` Hiroshi Doyu
2014-06-26 20:49 ` [RFC 05/10] ARM: tegra: Add memory controller on Tegra124 Thierry Reding
2014-06-26 20:49 ` [RFC 06/10] ARM: tegra: tegra124: Enable IOMMU for display controllers Thierry Reding
2014-06-26 20:49 ` [RFC 07/10] ARM: tegra: tegra124: Enable IOMMU for SDMMC controllers Thierry Reding
2014-06-26 20:49 ` [RFC 08/10] ARM: tegra: Select ARM_DMA_USE_IOMMU Thierry Reding
2014-06-26 20:49 ` [RFC 09/10] drm/tegra: Add IOMMU support Thierry Reding
2014-06-27 9:46 ` Hiroshi DOyu
2014-06-27 10:54 ` Arnd Bergmann
2014-06-27 11:03 ` Hiroshi Doyu
2014-06-27 10:58 ` Thierry Reding
2014-09-30 18:48 ` Sean Paul
2014-10-01 15:54 ` Sean Paul
2014-10-02 8:39 ` Thierry Reding
2014-11-05 9:50 ` Thierry Reding
2014-11-05 10:26 ` Thierry Reding
2014-06-26 20:49 ` [RFC 10/10] mmc: sdhci-tegra: " Thierry Reding
2014-06-27 9:46 ` Hiroshi DOyu
2014-06-27 11:01 ` Thierry Reding
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