From: will.deacon@arm•com (Will Deacon)
To: linux-arm-kernel@lists•infradead.org
Subject: [RFC PATCH 0/2] irqchip: GIC: check and clear GIC interupt active status
Date: Fri, 11 Jul 2014 13:35:07 +0100 [thread overview]
Message-ID: <20140711123507.GE12899@arm.com> (raw)
In-Reply-To: <1405061177-43834-1-git-send-email-sdu.liu@huawei.com>
[adding Marc]
On Fri, Jul 11, 2014 at 07:46:15AM +0100, Liu Hua wrote:
> For this version of GIC codes, kernel assumes that all the interrupt
> status of GIC is inactive. So the kernel does not check this when
> booting.
>
> This is no problem on must sitations. But when kdump is deplayed.
> And a panic occurs when a interrupt is being handled (may be PPI
> and SPI). We have no chance to write relative bit to GICC_EOIR.
> So this interrupt remains active. And GIC will not deliver this
> type interrupt to cpu interface. And the capture kernel may
> fail to boot becase of lacking of certain interrupt (such as timer
> interupt).
>
>
> I glanced over the GIC Architecture Specification, but did not
> find a simple way to deactive state of all interrupts. For GICv1,
> I can only deal with one abnormal interrupt state one time. For
> GICv2, I can deactive 32 one time.
>
>
> So guys, Do you know a better way to do that?
What happens if, in the crash kernel, you disable the CPU interfaces
(GICC_CTLR.ENABLE) then disable the distributor (GICD_CTLR.ENABLE) before
enabling everything again in the reverse order? Is that enough to cause the
GIC to drop any active states? It's not clear to me from a quick look at
the TRM.
Will
next prev parent reply other threads:[~2014-07-11 12:35 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-11 6:46 [RFC PATCH 0/2] irqchip: GIC: check and clear GIC interupt active status Liu Hua
2014-07-11 6:46 ` [RFC PATCH 1/2] irqchip: GIC: introduce ICPIDR2 register interface Liu Hua
2014-07-11 6:46 ` [RFC PATCH 2/2] irqchip: GIC: introduce method to deactive interupts Liu Hua
2014-07-11 12:35 ` Will Deacon [this message]
2014-07-14 3:22 ` [RFC PATCH 0/2] irqchip: GIC: check and clear GIC interupt active status Liu hua
2014-07-14 9:57 ` Will Deacon
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