Subject: [PATCH 12/13] cpufreq: Add cpufreq driver for Tegra124

From: [email-masked] (Thierry Reding)
Date: Fri, 11 Jul 2014 17:15:02 +0200

On Fri, Jul 11, 2014 at 06:11:41PM +0300, Tuomas Tynkkynen wrote:
> On 11/07/14 17:57, Thierry Reding wrote:
> 
> >>I don't think that's going to work? The voltage scaling is handled in hw.
> >
> >Do we have to handle it in hardware or can we opt to do it in software,
> >too?
> >
> 
> With the PLLX, voltage scaling is done entirely in SW. With the DFLL,
> it's possible to stay in open-loop mode and do it in SW, but there's
> not much point in that.

It's kind of ugly how we need to pass the address of the PMU and the
offset of the voltage control register to the DFLL which will then
initiate I2C transactions itself. I'm wondering if that plays well with
the I2C traffic originating from within the kernel.

Thierry
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