From: will.deacon@arm•com (Will Deacon)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH 0/4] ARM: perf: Support i.MX53
Date: Tue, 29 Jul 2014 13:52:31 +0100 [thread overview]
Message-ID: <20140729125231.GM9245@arm.com> (raw)
In-Reply-To: <20140729123256.13347.79778.stgit@localhost>
Hi Martin,
On Tue, Jul 29, 2014 at 01:32:56PM +0100, Martin Fuzzey wrote:
> This series enables hardware performance counters on the i.MX53 SoC
>
> This requires setting registers at both the ARM V7 core level
> and the i.MX53 SoC level.
>From a quick look at the patches, it sounds like you're booting in secure
mode and are trying to use perf there. Whilst I understand that you may want
to do this, I don't think the code you currently have is quite right:
- It accesses the SDER unconditionally, which is undefined for non-secure
modes.
- It adds yet more callbacks to arm_pmu_platdata
Instead, how about we add a new property on the PMU node that says it
requires secure access, then we use that to configuer SDER in the perf code.
Then you can do your SoC-specific magic as part of the runtime PM hooks we
already have (it looks like enabled/disabling a clock really).
Will
next prev parent reply other threads:[~2014-07-29 12:52 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-29 12:32 [PATCH 0/4] ARM: perf: Support i.MX53 Martin Fuzzey
2014-07-29 12:32 ` [PATCH 1/4] ARM: perf: Set suniden bit Martin Fuzzey
2014-07-29 12:33 ` [PATCH 2/4] ARM: perf: Add platform specific start/stop callbacks Martin Fuzzey
2014-07-29 12:33 ` [PATCH 3/4] ARM: i.MX53: Add Soc specific PMU setup Martin Fuzzey
2014-07-29 12:33 ` [PATCH 4/4] ARM: dts: i.MX53: Add PMU DT entry Martin Fuzzey
2014-07-29 12:52 ` Will Deacon [this message]
2014-07-29 16:40 ` [PATCH 0/4] ARM: perf: Support i.MX53 Martin Fuzzey
2014-07-30 10:46 ` Will Deacon
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