Subject: [PATCH v4] devicetree: Add generic IOMMU device tree bindings

From: [email-masked] (Thierry Reding)
Date: Thu, 31 Jul 2014 12:09:06 +0200

On Wed, Jul 30, 2014 at 07:18:42PM +0100, Mark Rutland wrote:
[...]
> > >> +
> > >> +Multiple-master IOMMU with configurable DMA window:
> > >> +---------------------------------------------------
> > >> +
> > >> +     / {
> > >> +             #address-cells = <1>;
> > >> +             #size-cells = <1>;
> > >> +
> > >> +             iommu {
> > >> +                     /* master ID, address and length of DMA window */
> > >> +                     #iommu-cells = <4>;
> > >> +             };
> > >> +
> > >> +             master {
> > >> +                     /* master ID 42, 4 GiB DMA window starting at 0 */
> > >> +                     iommus = <&/iommu  42  0  0x1 0x0>;
> > >
> > > Is this that window is from the POV of the master, i.e. the master can
> > > address 0x0 to 0xffffffff when generating transactions, and these get
> > > translated somehow?
> > >
> > > Or is this the physical addresses to allocate to the master?
> > 
> > It needs to be clarified in the documentation, but as far as I know it
> > is the DMA address space that is used.
> 
> Ok. So that's pre-translation, from the POV of the master?

Correct. It represents the window of the IOMMU's addressable I/O virtual
address space that should be assigned to this particular master.

> If we don't have that knowledge about the master already (e.g. based on
> the compatible string), surely we always need that information in a
> given iommu-specifier format? Otherwise certain iommus won't be able to
> handle masters with limited addressing only due to limitations of their
> binding.

This is only used for what's often called a windowed IOMMU. Many IOMMUs
(non-windowed) typically allow only a complete address space to be
assigned to a master without additional control over subregions. So this
is really a property/capability of the IOMMU rather than the masters
themselves.

There are already other means to respect the addressing limitations of
masters. We typcially use a device's DMA mask for this, and it's natural
to reuse that for I/O virtual addresses since they will in fact take the
place of physical addresses for the master when translation is enabled.

Thierry
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