Subject: [PATCH 1/7] clk: sunxi: Add post clk divider for factor clocks

From: [email-masked] (Maxime Ripard)
Date: Thu, 11 Sep 2014 22:36:49 +0200

On Sat, Sep 06, 2014 at 06:47:22PM +0800, Chen-Yu Tsai wrote:
> Some factor clocks, mostly PLLs, have an extra fixed divider just before
> the clock output. Add an option to the factor clk driver config data to
> specify this divider.
> 
> Signed-off-by: Chen-Yu Tsai <[email-masked]>

Acked-by: Maxime Ripard <[email-masked]>

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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