Subject: [PATCH 2/7] clk: sunxi: Fix PLL6 calculation on sun6i

From: [email-masked] (Maxime Ripard)
Date: Thu, 11 Sep 2014 22:38:25 +0200

On Sat, Sep 06, 2014 at 06:47:23PM +0800, Chen-Yu Tsai wrote:
> The N factor for PLL6 counts from 1 to 32, as specified in the A23
> manual, and shown in Allwinner's original A31 code.
> 
> Also the PLL6 factors alone calculate the clock rate for PLL6x2, not
> the normal halved output for PLL6. This is what the factors clk
> .recalc_rate callback expects.
> 
> This patch fixes the N factor in the clock driver, and adds a post
> PLL divider of 2 to calculate the rate for PLL6.
> 
> A further patch (to the DT) should add a fixed-factor x2 clock as
> the PLL6x2 output.
> 
> Signed-off-by: Chen-Yu Tsai <[email-masked]>

Acked-by: Maxime Ripard <[email-masked]>

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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