From: will.deacon@arm•com (Will Deacon)
To: linux-arm-kernel@lists•infradead.org
Subject: [V8 1/2] irqchip: gic: Add support for multiple MSI for ARM64
Date: Mon, 22 Sep 2014 10:15:36 +0100 [thread overview]
Message-ID: <20140922091536.GB25809@arm.com> (raw)
In-Reply-To: <1411230698-8081-2-git-send-email-suravee.suthikulpanit@amd.com>
Hi Suravee,
Just a few minor comments.
On Sat, Sep 20, 2014 at 05:31:37PM +0100, suravee.suthikulpanit at amd.com wrote:
> From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd•com>
>
> This patch implelments the ARM64 version of arch_setup_msi_irqs(),
> which does not return 1 for when PCI_CAP_ID_MSI and nvec > 1.
s/implelments/implements/
> Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd•com>
> Acked-by: Marc Zyngier <Marc.Zyngier@arm•com>
> Cc: Mark Rutland <Mark.Rutland@arm•com>
> Cc: Jason Cooper <jason@lakedaemon•net>
> Cc: Catalin Marinas <Catalin.Marinas@arm•com>
> Cc: Will Deacon <Will.Deacon@arm•com>
> ---
> arch/arm64/kernel/Makefile | 1 +
> arch/arm64/kernel/msi.c | 41 +++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 42 insertions(+)
> create mode 100644 arch/arm64/kernel/msi.c
>
> diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
> index df7ef87..a921c42 100644
> --- a/arch/arm64/kernel/Makefile
> +++ b/arch/arm64/kernel/Makefile
> @@ -29,6 +29,7 @@ arm64-obj-$(CONFIG_ARM64_CPU_SUSPEND) += sleep.o suspend.o
> arm64-obj-$(CONFIG_JUMP_LABEL) += jump_label.o
> arm64-obj-$(CONFIG_KGDB) += kgdb.o
> arm64-obj-$(CONFIG_EFI) += efi.o efi-stub.o efi-entry.o
> +arm64-obj-$(CONFIG_PCI_MSI) += msi.o
>
> obj-y += $(arm64-obj-y) vdso/
> obj-m += $(arm64-obj-m)
> diff --git a/arch/arm64/kernel/msi.c b/arch/arm64/kernel/msi.c
> new file mode 100644
> index 0000000..a295862
> --- /dev/null
> +++ b/arch/arm64/kernel/msi.c
> @@ -0,0 +1,41 @@
> +/*
> + * ARM64 architectural MSI implemention
> + *
> + * Support for Message Signalelled Interrupts for systems that
> + * implement ARM Generic Interrupt Controller: GICv2m.
You can drop the GICv2M reference here, as there's not really anything
GIC-specific in this file.
> + * Copyright (C) 2014 Advanced Micro Devices, Inc.
> + * Authors: Suravee Suthikulpanit <suravee.suthikulpanit@amd•com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published
> + * by the Free Software Foundation.
> + */
> +
> +#include <linux/irq.h>
> +#include <linux/msi.h>
> +#include <linux/pci.h>
> +
> +/*
> + * ARM64 function for seting up MSI irqs.
> + * Based on driver/pci/msi.c: arch_setup_msi_irqs().
> + *
> + * Note:
> + * Current implementation assumes that all interrupt controller used in
> + * ARM64 architecture _MUST_ supports multi-MSI.
I think you can remove this comment, to be honest.
> + */
> +int arm64_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
> +{
Shouldn't this be called arch_setup_msi_irqs, since the intention is that
you override the weak symbol?
> + struct msi_desc *entry;
> + int ret;
> +
> + list_for_each_entry(entry, &dev->msi_list, list) {
> + ret = arch_setup_msi_irq(dev, entry);
> + if (ret < 0)
> + return ret;
> + if (ret > 0)
> + return -ENOSPC;
When does this function ever return a value > 0?
Will
next prev parent reply other threads:[~2014-09-22 9:15 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-20 16:31 [V8 0/2] irqchip: gic: Introduce ARM GICv2m MSI(-X) support suravee.suthikulpanit at amd.com
2014-09-20 16:31 ` [V8 1/2] irqchip: gic: Add support for multiple MSI for ARM64 suravee.suthikulpanit at amd.com
2014-09-22 9:15 ` Will Deacon [this message]
2014-09-22 23:08 ` Thomas Gleixner
2014-09-23 17:04 ` Suravee Suthikulpanit
2014-09-23 21:33 ` Thomas Gleixner
2014-09-20 16:31 ` [V8 2/2] irqchip: gicv2m: Add supports for ARM GICv2m MSI(-X) suravee.suthikulpanit at amd.com
2014-09-22 17:37 ` Mark Rutland
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