From: will.deacon@arm•com (Will Deacon)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH 2/2] iommu/arm-smmu: add support for iova_to_phys through ATS1PR
Date: Mon, 22 Sep 2014 16:26:14 +0100 [thread overview]
Message-ID: <20140922152614.GP25809@arm.com> (raw)
In-Reply-To: <1410460244-18943-3-git-send-email-mitchelh@codeaurora.org>
Hi Mitch,
On Thu, Sep 11, 2014 at 07:30:44PM +0100, Mitchel Humpherys wrote:
> Currently, we provide the iommu_ops.iova_to_phys service by doing a
> table walk in software to translate IO virtual addresses to physical
> addresses. On SMMUs that support it, it can be useful to ask the SMMU
> itself to do the translation. This can be used to warm the TLBs for an
> SMMU. It can also be useful for testing and hardware validation.
>
> Since the address translation registers are optional on SMMUv2, only
> enable hardware translations when using SMMUv1 or when SMMU_IDR0.S1TS=1
> and SMMU_IDR0.ATOSNS=0, as described in the ARM SMMU v1-v2 spec.
[...]
> +static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
> + dma_addr_t iova)
> +{
> + struct arm_smmu_domain *smmu_domain = domain->priv;
> + struct arm_smmu_device *smmu = smmu_domain->smmu;
> + struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
> + struct device *dev = smmu->dev;
> + void __iomem *cb_base;
> + u32 tmp;
> + u64 phys;
> +
> + cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
> +
> + if (smmu->version == 1) {
> + u32 reg = iova & ~0xFFF;
> + writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_LO);
> + } else {
> + u32 reg = iova & ~0xFFF;
> + writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_LO);
> + reg = (iova & ~0xFFF) >> 32;
> + writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_HI);
> + }
> +
> + if (readl_poll_timeout(cb_base + ARM_SMMU_CB_ATSR, tmp,
> + !(tmp & ATSR_ACTIVE), 10, ATSR_LOOP_TIMEOUT)) {
> + dev_err(dev,
> + "iova to phys timed out on 0x%pa for %s. Falling back to software table walk.\n",
> + &iova, dev_name(dev));
dev_err already prints the device name.
> + return arm_smmu_iova_to_phys_soft(domain, iova);
> + }
> +
> + phys = readl_relaxed(cb_base + ARM_SMMU_CB_PAR_LO);
> + phys |= ((u64) readl_relaxed(cb_base + ARM_SMMU_CB_PAR_HI)) << 32;
> +
> + if (phys & CB_PAR_F) {
> + dev_err(dev, "translation fault on %s!\n", dev_name(dev));
> + dev_err(dev, "PAR = 0x%llx\n", phys);
> + }
> + phys = (phys & 0xFFFFFFF000ULL) | (iova & 0x00000FFF);
How does this work for 64k pages?
Will
next prev parent reply other threads:[~2014-09-22 15:26 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-11 18:30 [PATCH 0/2] iommu/arm-smmu: hard iova_to_phys Mitchel Humpherys
2014-09-11 18:30 ` [PATCH 1/2] iopoll: Introduce memory-mapped IO polling macros Mitchel Humpherys
2014-09-22 15:23 ` Will Deacon
2014-09-11 18:30 ` [PATCH 2/2] iommu/arm-smmu: add support for iova_to_phys through ATS1PR Mitchel Humpherys
2014-09-22 15:26 ` Will Deacon [this message]
2014-09-24 1:12 ` Mitchel Humpherys
2014-09-24 16:37 ` Will Deacon
2014-09-24 20:34 ` Mitchel Humpherys
2014-09-26 10:24 ` Will Deacon
2014-09-26 17:20 ` Mitchel Humpherys
2014-09-11 18:53 ` [PATCH 0/2] iommu/arm-smmu: hard iova_to_phys Mitchel Humpherys
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