Subject: [PATCH 5/7] ARM: mvebu: Enable Performance Monitor Unit on Armada 375 SoC

From: [email-masked] (Mark Rutland)
Date: Thu, 23 Oct 2014 14:18:40 +0100

On Thu, Oct 23, 2014 at 01:07:31PM +0100, Thomas Petazzoni wrote:
> Dear Ezequiel Garcia,
> 
> On Thu, 23 Oct 2014 08:51:27 -0300, Ezequiel Garcia wrote:
> 
> > > On Wed, 22 Oct 2014 19:16:42 -0300, Ezequiel Garcia wrote:
> > > 
> > >> The <mpic 3> is a per CPU interrupt.
> > >>
> > >> Actually, the interrupt contains more than just PMU events, it contains
> > >> a summary of several CPU events: Perf counters for each CPU, Power
> > >> management interrupts for each CPU, L2 cache interrupt, among others.
> > > 
> > > This is kind of a side discussion but if this <mpic 3> interrupts does
> > > much more than PMU events, then we should implement a separate irqchip
> > > driver for this, to "demultiplex" the events notified by this interrupt.
> > 
> > Oh, I didn't realize this was possible.
> 
> The only trick is that it can't be a separate DT node, because the
> registers that contains the mask/cause informations for the events
> notified by <mpic 3> belongs to the MPIC registers area.
> 
> Not sure how to handle that, maybe Mark will have some suggestions.

I'm not sure I follow why you would need a separate irqchip driver. Why
can't this live in the existing mpic driver?

Thanks,
Mark.