Subject: [PATCH v3 2/6] clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output

From: [email-masked] (Maxime Ripard)
Date: Sun, 16 Nov 2014 18:07:24 +0100

On Thu, Nov 13, 2014 at 02:08:31AM +0800, Chen-Yu Tsai wrote:
> Some clock modules on the A31 use PLL6x2 as one of their inputs.
> This patch changes the PLL6 implementation for A31 to a divs clock,
> i.e. clock with multiple outputs that have different dividers.
> The first output will be the normal PLL6 output, and the second
> will be PLL6x2.
> 
> This patch fixes the PLL6 N factor in the clock driver, and removes
> any /2 dividers in the PLL6 factors clock part. The N factor counts
> from 1 to 32, mapping to values 0 to 31, as shown in the A31 manual.
> 
> Signed-off-by: Chen-Yu Tsai <[email-masked]>

Merged, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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