Subject: [PATCH 3/4] devicetree: bindings: Add defeature-repeated-start property for Cadence I2C

From: [email-masked] (Wolfram Sang)
Date: Tue, 2 Dec 2014 13:52:03 +0100

> >> +  - defeature-repeated-start: Include this property to defeature repeated start
> >> +                           This defeature is due to a few bugs in the
> >> +                           I2C controller.
> >> +                           Completion interrupt after a read/receive
> >> +                           operation is NOT obtained if HOLD bit is set
> >> +                           at that time. Because of this bug, repeated start
> >> +                           will only work if there are no transfers following
> >> +                           a read/receive transfer.
> >> +                           If HOLD is held for long without a transfer,
> >> +                           invalid read transactions are generated by the
> >> +                           controller due to a HW timeout related bug.
> >
> > I'm not keen on the name; it sounds like we're disabling a feature
> > rather than describing the problem (and "defeature" is not a common
> > term in this sense, "disable" would be better).
> >
> > It sounds like there are two issues with staying in the HOLD state? Lost
> > completion IRQs and a separate HW timeout bug? Or are the two related?
> >
> 
> Yes, there are two issues here and they are not related.
> But a combination of both is leading to not using repeated start.
> The intention was to defeature except that it works in some scenarios
> (such as a typical write+read in that order with repeated start)
> and there are people who already use the driver with slaves that need this.

That should not be handled using a binding. If you get a transfer (at
runtime) with criteria you don't support, return with -EOPNOTSUPP from
the master xfer routine.

That being said, the number of broken/not-fully-compliant I2C
controllers has increased a lot recent times (why can't we just use the
established old ones?). Maybe we will have core support for a subset of
I2C (wr+rd) in the future, but that's still ahead...

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