Subject: [PATCH v4 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining

From: [email-masked] (Brian Norris)
Date: Sat, 28 Feb 2015 01:01:22 -0800

On Wed, Feb 18, 2015 at 11:32:07AM +0100, Maxime Ripard wrote:
> The NDDB register holds the data that are needed by the read and write
> commands.
> 
> However, during a read PIO access, the datasheet specifies that after each 32
> bytes read in that register, when BCH is enabled, we have to make sure that the
> RDDREQ bit is set in the NDSR register.
> 
> This fixes an issue that was seen on the Armada 385, and presumably other mvebu
> SoCs, when a read on a newly erased page would end up in the driver reporting a
> timeout from the NAND.
> 
> Cc: <[email-masked]> # v3.14
> Signed-off-by: Maxime Ripard <[email-masked]>

Pushed this one to linux-mtd.git. I'll try to get it out in the 4.0
cycle. I assume patch 2 (the DT addition) will go through arm-soc.

Brian