Subject: [PATCH v2] clk: exynos4: Fix wrong clock for Exynos4x12 ADC

From: [email-masked] (Stephen Boyd)
Date: Tue, 21 Jul 2015 15:42:36 -0700

On 06/12, Krzysztof Kozlowski wrote:
> The TSADC gate clock was used in Exynos4x12 DTSI for exynos-adc driver.
> However TSADC is present only on Exynos4210 so on Trats2 board (with
> Exynos4412 SoC) the exynos-adc driver could not be probed:
>    ERROR: could not get clock /adc at 126C0000:adc(0)
>    exynos-adc 126c0000.adc: failed getting clock, err = -2
>    exynos-adc: probe of 126c0000.adc failed with error -2
> 
> Instead on Exynos4x12 SoCs the main clock used by Analog to Digital
> Converter is located in different register and it is named in datasheet
> as PCLK_ADC. Regardless of the name the purpose of this PCLK_ADC clock
> is the same as purpose of TSADC from Exynos4210.
> 
> The patch adds gate clock for Exynos4x12 using the proper register so
> backward compatibility is preserved. This fixes the probe of exynos-adc
> driver on Exynos4x12 boards and allows accessing sensors connected to it
> on Trats2 board (ntc,ncp15wb473 AP and battery thermistors).
> 
> Signed-off-by: Krzysztof Kozlowski <[email-masked]>
> Cc: <[email-masked]>
> Fixes: c63c57433003 ("ARM: dts: Add ADC's dt data to read raw data for exynos4x12")
> Link: https://lkml.org/lkml/2015/6/11/85
> 

Did you want clk maintainers to apply this? The To: list is not
helping so I'm not sure what's going on and it seems to have
slipped through the cracks.

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