From: catalin.marinas@arm•com (Catalin Marinas)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH 06/10] arm64: tlbflush: avoid flushing when fullmm == 1
Date: Mon, 5 Oct 2015 18:18:43 +0100 [thread overview]
Message-ID: <20151005171842.GE5557@MBP.local> (raw)
In-Reply-To: <20151005163313.GC3211@arm.com>
On Mon, Oct 05, 2015 at 05:33:13PM +0100, Will Deacon wrote:
> On Tue, Sep 29, 2015 at 10:29:58AM +0100, Catalin Marinas wrote:
> > On Thu, Sep 17, 2015 at 01:50:15PM +0100, Will Deacon wrote:
> > > The TLB gather code sets fullmm=1 when tearing down the entire address
> > > space for an mm_struct on exit or execve. Given that the ASID allocator
> > > will never re-allocate a dirty ASID, this flushing is not needed and can
> > > simply be avoided in the flushing code.
> > >
> > > Signed-off-by: Will Deacon <will.deacon@arm•com>
> > > ---
> > > arch/arm64/include/asm/tlb.h | 26 +++++++++++++++-----------
> > > 1 file changed, 15 insertions(+), 11 deletions(-)
> > >
> > > diff --git a/arch/arm64/include/asm/tlb.h b/arch/arm64/include/asm/tlb.h
> > > index d6e6b6660380..ffdaea7954bb 100644
> > > --- a/arch/arm64/include/asm/tlb.h
> > > +++ b/arch/arm64/include/asm/tlb.h
> > > @@ -37,17 +37,21 @@ static inline void __tlb_remove_table(void *_table)
> > >
> > > static inline void tlb_flush(struct mmu_gather *tlb)
> > > {
> > > - if (tlb->fullmm) {
> > > - flush_tlb_mm(tlb->mm);
> > > - } else {
> > > - struct vm_area_struct vma = { .vm_mm = tlb->mm, };
> > > - /*
> > > - * The intermediate page table levels are already handled by
> > > - * the __(pte|pmd|pud)_free_tlb() functions, so last level
> > > - * TLBI is sufficient here.
> > > - */
> > > - __flush_tlb_range(&vma, tlb->start, tlb->end, true);
> > > - }
> > > + struct vm_area_struct vma = { .vm_mm = tlb->mm, };
> > > +
> > > + /*
> > > + * The ASID allocator will either invalidate the ASID or mark
> > > + * it as used.
> > > + */
> > > + if (tlb->fullmm)
> > > + return;
> >
> > BTW, do we actually need this flush_tlb_mm() with the current ASID
> > allocator? It doesn't reuse old ASIDs either before a full TLBI (just
> > trying to remember if we had any logic; or maybe it was needed before
> > non-lazy __pte_free_tlb).
>
> I'm afraid I don't follow you here. This diff is removing the flush_tlb_mm
> because, as you point out, it's no longer needed.
I don't think you are missing anything, just wondering why we had it
before (probably forgot to remove it when the non-lazy __pte_free_tlb
was added).
--
Catalin
next prev parent reply other threads:[~2015-10-05 17:18 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-17 12:50 [PATCH 00/10] arm64 switch_mm improvements Will Deacon
2015-09-17 12:50 ` [PATCH 01/10] arm64: mm: remove unused cpu_set_idmap_tcr_t0sz function Will Deacon
2015-09-17 12:50 ` [PATCH 02/10] arm64: proc: de-scope TLBI operation during cold boot Will Deacon
2015-09-17 12:50 ` [PATCH 03/10] arm64: flush: use local TLB and I-cache invalidation Will Deacon
2015-09-17 12:50 ` [PATCH 04/10] arm64: mm: rewrite ASID allocator and MM context-switching code Will Deacon
2015-09-29 8:46 ` Catalin Marinas
2015-10-05 16:31 ` Will Deacon
2015-10-05 17:16 ` Catalin Marinas
2015-09-17 12:50 ` [PATCH 05/10] arm64: tlbflush: remove redundant ASID casts to (unsigned long) Will Deacon
2015-09-17 12:50 ` [PATCH 06/10] arm64: tlbflush: avoid flushing when fullmm == 1 Will Deacon
2015-09-29 9:29 ` Catalin Marinas
2015-10-05 16:33 ` Will Deacon
2015-10-05 17:18 ` Catalin Marinas [this message]
2015-09-17 12:50 ` [PATCH 07/10] arm64: switch_mm: simplify mm and CPU checks Will Deacon
2015-09-17 12:50 ` [PATCH 08/10] arm64: mm: kill mm_cpumask usage Will Deacon
2015-09-17 12:50 ` [PATCH 09/10] arm64: tlb: remove redundant barrier from __flush_tlb_pgtable Will Deacon
2015-09-17 12:50 ` [PATCH 10/10] arm64: mm: remove dsb from update_mmu_cache Will Deacon
2015-09-29 9:55 ` [PATCH 00/10] arm64 switch_mm improvements Catalin Marinas
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