Subject: [PATCH 04/14] clk: sunxi: add ahb1 clock for A83T

From: [email-masked] (Maxime Ripard)
Date: Thu, 4 Feb 2016 09:01:09 +0100

On Thu, Feb 04, 2016 at 02:06:45PM +0800, Vishnu Patekar wrote:
> Hello Maxime,
> 
> 
> On Tue, Feb 2, 2016 at 9:17 PM, Maxime Ripard
> <[email-masked]> wrote:
> > Hi,
> >
> > On Sun, Jan 31, 2016 at 09:20:56AM +0800, Vishnu Patekar wrote:
> >> AHB1 on A83T is similar to ahb1 on A31, except parents are different.
> >> clock index 0b1x is PLL6.
> >>
> >> Signed-off-by: Vishnu Patekar <[email-masked]>
> >
> > If the clock is the same but the parents are different, then we don't
> > need to duplicate all the logic. Simply add the number of parents to
> > mux_data, and you're all set.
> 
> Problem here is: parent 0b10 for A31 ahb1 is AXI, 0b11 is pll6/pre_div.
> 0b10 and 0b11 is pll6/pre_div.
> So, just adding number of parents to mux_data will not solve problem.

Is anyone using 0b11 ? Can't we just ignore it?

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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