Subject: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

From: [email-masked] (Marc Zyngier)
Date: Mon, 7 Mar 2016 09:50:21 +0000

On Mon, 7 Mar 2016 11:36:22 +0800
Minghuan Lian <[email-masked]> wrote:

> Some kind of NXP Layerscape SoC provides a MSI
> implementation which uses two SCFG registers MSIIR and
> MSIR to support 32 MSI interrupts for each PCIe controller.
> The patch is to support it.
> 
> Signed-off-by: Minghuan Lian <[email-masked]>

Acked-by: Marc Zyngier <[email-masked]>

The DT binding still needs an Ack from the DT maintainers though (cc'd).

	M.
-- 
Jazz is not dead. It just smells funny.