Subject: [PATCH] dma: sun4i: expose block size and wait cycle configuration to DMA users

From: [email-masked] (Vinod Koul)
Date: Fri, 11 Mar 2016 11:56:07 +0530

On Wed, Mar 09, 2016 at 12:06:27PM +0100, Boris Brezillon wrote:
> On Tue, 8 Mar 2016 08:25:47 +0530
> Vinod Koul <[email-masked]> wrote:
> > 
> > Why does dmaengine need to wait? Can you explain that
> 
> I don't have an answer for that one, but when I set WAIT_CYCLES to 1
> for the NAND use case it does not work. So I guess it is somehow
> related to how the DRQ line is controlled on the device side...

Is the WAIT cycle different for different usages or same for all
usages/channels?

-- 
~Vinod