Subject: [RESEND PATCH v10 2/6] clk: hisilicon: add CRG driver for hi3519 soc

From: [email-masked] (Stephen Boyd)
Date: Fri, 15 Apr 2016 17:41:30 -0700

On 04/15, Jiancheng Xue wrote:
> Hi,
> 
> On 2016/3/31 16:10, Jiancheng Xue wrote:
> > From: Jiancheng Xue <[email-masked]>
> > 
> > The CRG(Clock and Reset Generator) block provides clock
> > and reset signals for other modules in hi3519 soc.
> > 
> > Signed-off-by: Jiancheng Xue <[email-masked]>
> > Acked-by: Rob Herring <[email-masked]>
> > Acked-by: Philipp Zabel <[email-masked]>
> > ---
> I hope this patchset can be merged through arch/arm tree
> The dts binding part has been acked by Rob Herring, and
> the reset part has been acked by Philipp Zabel. Could you
> help me to ack this whole clk patch? Please also let me
> know if this patch still have issues. Thank you very much!

Can I merge it through clk tree and make a stable branch to pull
through arm-soc? I assume another patch is coming but it's good
to get clarity before then.

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