Subject: [PATCH v3 03/19] clk: sunxi: Add PLL3 clock

From: [email-masked] (Maxime Ripard)
Date: Tue, 19 Apr 2016 11:18:23 +0200

On Fri, Apr 15, 2016 at 03:34:41PM -0700, Stephen Boyd wrote:
> On 03/23, Maxime Ripard wrote:
> > The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
> > PLL7, clocked from a 3MHz oscillator, that drives the display related
> > clocks (GPU, display engine, TCON, etc.)
> > 
> > Add a driver for it.
> > 
> > Acked-by: Rob Herring <[email-masked]>
> > Acked-by: Chen-Yu Tsai <[email-masked]>
> > Signed-off-by: Maxime Ripard <[email-masked]>
> > ---
> 
> Acked-by: Stephen Boyd <[email-masked]>

Applied, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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