Subject: [PATCH 07/11] clk: imx6ul: fix pll clock parents

From: [email-masked] (Dong Aisheng)
Date: Sun, 12 Jun 2016 20:19:47 +0800

On Sun, Jun 12, 2016 at 07:52:04PM +0800, Dong Aisheng wrote:
> On Sun, Jun 12, 2016 at 07:43:53PM +0800, Shawn Guo wrote:
> > On Wed, Jun 08, 2016 at 10:33:36PM +0800, Dong Aisheng wrote:
> > > pllx_bypass_src mux shouldn't be the parent of pllx clock
> > > since it's only valid when when pllx BYPASS bit is set.
> > > Thus it is actually one parent of pllx_bypass only.
> > > 
> > > Instead, pllx parent should be fixed to osc according to
> > > reference manual.
> > > Other plls have the same issue.
> > > 
> > > e.g. before fix, the pll tree is:
> > > osc                                      6            6    24000000          0 0
> > >    pll1_bypass_src                       0            0    24000000          0 0
> > >       pll1                               0            0   792000000          0 0
> > >          pll1_bypass                     0            0   792000000          0 0
> > >             pll1_sys                     0            0   792000000          0 0
> > > 
> > > After the fix, it's:
> > > osc                                      6            6    24000000          0 0
> > >    pll1                                  0            0   792000000          0 0
> > >       pll1_bypass                        0            0   792000000          0 0
> > >          pll1_sys                        0            0   792000000          0 0
> > > 
> > > Signed-off-by: Dong Aisheng <[email-masked]>
> > 
> > I squashed 7 ~ 11 into one patch and applied it, thanks.
> > 
> 
> I'm fine.
> Thanks
> 

You probably may need to change the patch title after merge.
clk: imx: fix pll clock parents

Regards
Dong Aisheng

> Regards
> Dong Aisheng
> 
> > Shawn
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