Subject: [PATCH 2/3] mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers

From: [email-masked] (Maxime Ripard)
Date: Thu, 21 Jul 2016 10:56:15 +0200

Hi,

On Wed, Jul 20, 2016 at 08:16:28PM +0200, Jean-Francois Moine wrote:
> The 'new timing mode' with 8 bits DDR works correctly when the NewTiming
> register is set.

What does that mode brings to the table?

> 
> Signed-off-by: Jean-Francois Moine <[email-masked]>
> ---
> Note about the 'new timing mode'.
> 
> This patch assumes that, when the new mode is used, the clock driver
> sets the mode select in the MMC clock and multiplies the clock rate
> by 2:
> - MMC side:
>   - with a timing 8 bits DDR at 50MHz, the MMC driver calls
>     clk_set_rate() with a rate 50*2 = 100MHz,
> - clock side:
>   - the clock driver sets the hardware MMC clock to 100*2 = 200MHz,
>   - setting the 'mode select' of the hardware MMC clock divides the
>     rate by 2,
> - MMC side:
>   - setting the MMC clock divider register to 1 divides the rate by 2.
> So, the final rate is 50MHz.

What happens if you actually want to set it to 100MHz?

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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