Subject: [PATCH v3 8/9] arm64: Refactor sysinstr exception handling

From: [email-masked] (Will Deacon)
Date: Wed, 7 Sep 2016 09:44:37 +0100

On Mon, Sep 05, 2016 at 10:58:28AM +0100, Suzuki K Poulose wrote:
> Right now we trap some of the user space data cache operations
> based on a few Errata (ARM 819472, 826319, 827319 and 824069).
> We need to trap userspace access to CTR_EL0, if we detect mismatched
> cache line size. Since both these traps share the EC, refactor
> the handler a little bit to make it a bit more reader friendly.
> 
> Cc: Andre Przywara <[email-masked]>
> Cc: Mark Rutland <[email-masked]>
> Cc: Will Deacon <[email-masked]>
> Cc: Catalin Marinas <[email-masked]>
> Signed-off-by: Suzuki K Poulose <[email-masked]>
> ---
>  arch/arm64/include/asm/esr.h | 76 ++++++++++++++++++++++++++++++++++++++------
>  arch/arm64/kernel/traps.c    | 73 +++++++++++++++++++++++++++---------------
>  2 files changed, 114 insertions(+), 35 deletions(-)

This looks fine to me, but I'd really like to see Andre's ack on the
refactoring of the errata workarounds.

Andre, can you take a look please?

Will