Subject: [PATCH V4 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table

From: [email-masked] (Thierry Reding)
Date: Mon, 7 Nov 2016 12:27:53 +0100

On Mon, Nov 07, 2016 at 09:30:00AM +0100, Mirza Krak wrote:
> From: Mirza Krak <[email-masked]>
> 
> Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which
> is max rate.
> 
> The maximum rate value of 92 MHz is pulled from the downstream L4T
> kernel.
> 
> Signed-off-by: Mirza Krak <[email-masked]>
> Tested-by: Marcel Ziswiler <[email-masked]>
> Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
> Acked-by: Jon Hunter <[email-masked]>
> ---
> 
> Changes in v2:
> - no changes
> 
> Changes in v3:
> - Added comment in commit message where I got the maximum rates from.
> 
> Changes in V4:
> - no changes

Applied, thanks.

Thierry
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