From: will.deacon@arm•com (Will Deacon)
To: linux-arm-kernel@lists•infradead.org
Subject: [QUESTION] Early Write Acknowledge for PCIe configuration space
Date: Mon, 9 Jan 2017 11:23:41 +0000 [thread overview]
Message-ID: <20170109112340.GB21398@arm.com> (raw)
In-Reply-To: <e085504e-74fd-e8be-8287-4baef88551c9@huawei.com>
On Mon, Jan 09, 2017 at 10:59:47AM +0000, John Garry wrote:
> On 06/01/2017 11:24, Arnd Bergmann wrote:
> >On Friday, January 6, 2017 11:15:22 AM CET John Garry wrote:
> >>[apologies if this has been queried before]
> >>
> >>Hi ARM guys,
> >>
> >>I have a question about the device memory attributes we assign for PCIe
> >>config space for arm64. Currently we use ioremap to map in the config
> >>space; this uses nGnRE, which means we enable Early Write Acknowledge.
> >>
> >>The ARMv8 ARM states that "ARM recommend that No Early Write Acknowledge
> >>Hint is used for PCIe configuration writes".
> >>
> >>I understand a problem with using E is in that configuration write is a
> >>non-post operation, which means the RP requires to get the completion
> >>ack from the EP The problem here is if CPU writes data to ECAM by E,
> >>complete will go back to CPU directly, and maybe at this point the write
> >>has not reached the EP.
> >>
> >>I believe that this may cause ordering issues in PCI read/write. In
> >>practice we use non-relaxed readl/writel to access config space, which
> >>include the synchronization barriers, which, *as I understand*, even if
> >>for full system domain, may be negated by the E attribute for PCIe.
> >
> >I don't think the barriers in readl/writel are enough here, in particular
> >the write barrier is *before* the access to synchronize DMAs
> >on RAM with MMIO accesses, which is a bit different from what you
> >have here.
> >
> >>So a question: why is the recommendation in the ARMv8 ARM ignored?
> >
> >Probably nobody thought about this properly in the Linux drivers. The
> >ARMv8 ARM sounds correct here.
> >
> >I/O space may have the same issue, as it also requires non-posted
> >accesses.
>
> Right, so our HW team's recommendation - from ARM's memory model and also
> PCIe order model - is that not only config space but also PCIe memory mapped
> IO has the same attribute (nE).
What's the rationale behind that recommendation?
Will
next prev parent reply other threads:[~2017-01-09 11:23 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-06 11:15 [QUESTION] Early Write Acknowledge for PCIe configuration space John Garry
2017-01-06 11:24 ` Arnd Bergmann
2017-01-06 11:42 ` Will Deacon
2017-02-08 18:35 ` Lorenzo Pieralisi
2017-02-09 11:30 ` Will Deacon
2017-02-09 11:42 ` Gabriele Paoloni
2017-02-09 14:38 ` Lorenzo Pieralisi
2017-02-09 14:53 ` Gabriele Paoloni
2017-01-09 10:59 ` John Garry
2017-01-09 11:23 ` Will Deacon [this message]
2017-01-09 11:52 ` Arnd Bergmann
2017-01-10 10:22 ` John Garry
2017-01-10 10:47 ` Gabriele Paoloni
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