Subject: [PATCH] virtio: Try to untangle DMA coherency

From: [email-masked] (Michael S. Tsirkin)
Date: Fri, 10 Feb 2017 19:16:10 +0200

On Thu, Feb 09, 2017 at 06:31:18PM +0000, Will Deacon wrote:
> On ARM (and other archs such as
> Power), having a mismatch between a cacheable and a non-cacheable mapping
> can result in a loss of coherency between the two (for example, if the
> non-cacheable gues accesses bypass the cache, but the cacheable host
> accesses allocate in the cache).

I guess it's an optimization to avoid cache snoops for non-cacheable accesses?

-- 
MST